Restrictions in input combinations of circuit?

Discussion in 'Homework Help' started by Gonzalo Armbrust, Oct 26, 2015.

  1. Gonzalo Armbrust

    Thread Starter New Member

    Jun 28, 2015
    16
    0
    I have a problem in which I am asked to " find any restrictions on the allowable input combinations on A and B"

    I have designed a next state truth table for the problem in the attachements, however i'm confused as to what exactly is a restriction. I noticed that for when A = 0, B=0, it oscillates between 0 and 1, and 1 and 0 when the Q current state variable is changed and the P (output) is changed. There is a similar case for when A = 1, and B=1. If i'm understanding this correctly then, would the restrictions be that A cannot be equal to 1 and B cannot be equal to zero when Q is equal to 1...? And also A and B cannot be equal to 1 when Q is equal to 0..?
     
  2. GopherT

    AAC Fanatic!

    Nov 23, 2012
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    The lighting of the afternoon sun coming into your window has not been fully captured by your camera. I suggest something with higher resolution. I can't stand looking at anything with such low resolution when I think about the beauty that was missed in your attempt to capture this moment with a measly 4.9Mb file.

    On the other hand, if you are just trying to ask for help, please use a low resolution image next time.
     
  3. Gonzalo Armbrust

    Thread Starter New Member

    Jun 28, 2015
    16
    0
    Here's the table I made, i'll just type it out:

    present state / Next state
    A | B | Q | Q | P (output)
    0 0 0 0 1
    0 0 1 0 1
    0 1 0 0 1
    0 1 1 1 0
    1 0 0 0 1
    1 0 1 0 1
    1 1 0 0 1
    1 1 1 1 0


    Assuming that the table is correct, what would the restrictions be?
    The circuit is just an S/R latch, with A and B fed into a NAND gate as the S input, and the value of B is the R input. I can post it if it's needed. P= Q'
     
  4. StayatHomeElectronics

    Well-Known Member

    Sep 25, 2008
    864
    40
    Do you know of any restrictions to the use of an S/R latch?
     
  5. MikeML

    AAC Fanatic!

    Oct 2, 2009
    5,450
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    What does the latch do if both Set and Reset are asserted?
     
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