Reset sequence interpretation, crystals

Discussion in 'Embedded Systems and Microcontrollers' started by Pootworm, Jan 3, 2008.

  1. Pootworm

    Thread Starter Member

    May 18, 2007
    29
    0
    Hey all,

    I'm having trouble interpreting what the following means (this is from the at89c51snd1c datasheet, from Atmel).

    What does that even mean? Higher than the highest allowed and lower than the lowest allowed?

    Thanks in advance.
     
  2. hgmjr

    Moderator

    Jan 28, 2005
    9,030
    214
    I think what it is trying to say is that the amplitude of the signal on xtal-in must be great enough such that its positive most excursion is greater than VIH and that its negative most excursion is less than VIL.

    hgmjr
     
  3. beenthere

    Retired Moderator

    Apr 20, 2004
    15,815
    282
    Any voltage above VIH will be sensed as a logic HIGH, and anything lower than VIL will be sensed as a logic LOW.
     
  4. Papabravo

    Expert

    Feb 24, 2006
    10,135
    1,786
    If you look at the startup of a crystal oscillator you will see it go from a steady value of Vdd/2 to small oscillations which increase in magnitude until they are outside the specified range.

    The interpretation is that Vdd is above a certain value and the oscillator is running.

    Things to watch out for are a slowly rising Vdd, and to much or too little load capacitance on the crystal.
     
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