Requesting help| TI CD4094BE SIPO shift register problem

Discussion in 'The Projects Forum' started by Jordy121, Oct 19, 2013.

  1. Jordy121

    Thread Starter New Member

    Oct 19, 2013
    1
    0
    Hi there, I am using the CD4094BE SIPO shift register for a project of mine (I am an EE student), and i have this issue that when
    data is low and i am giving 1 CP Q1-Q8 all turn to logic low instead of just shifting one LOW to Q1.
    when shifting HIGH all is working well, my only problem is when data is low and CP is given all OUTPUTS turn LOW at once.

    I tried reducing the CAP on the CK line to 22nF and add a 100nF decoupling cap near the IC still no luck... both schematics are attached here, please help!
     
  2. ericgibbs

    AAC Fanatic!

    Jan 29, 2010
    2,501
    380
    Hi,
    The rising edge of the Clock input is too slow, its possible that you could get multiple clocking due the slow rise.

    I would advise that you use a Schmitt trigger IC to sharpen the rise time of the clock, add your switch noise filter on the Schmitt input.

    Also I would advise a pull up resistor on the 'D' data input.

    E.
     
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