Hi All,

I have been taking some traces today of my 100MHz PCIe reference CLK, which does unfortunately have a 19" run down my board.

I have been taking traces considering whether or not I should buffer it or take any other special precautions in my next revision.

What I have been confronted with is really confusing me..... I'd really appreciate a second opinion.

I have marked up the attached differential traces I have taken, where you can see the 'multi sample' trace at the driver end, as well as the receiving end. The receiving end looks quite good (odd for a 19" trace with some impedance mismatches along the way), however wtf is going on at the driver!?

I was expecting it to, as per usual, have a brief moment where the reflections fight the driver but then the driver to eventually dominate, however this does not seem to occur and the reflection seems to win!? The feck? I'm confused?

Thanks in advance,

James

 

The typical signal propagation signal on a PC board is about 2ns/ft so a 19" line will take about 6ns for the reflection to return to the source. I'm not seeing anything at that point in time so there is apparently no significant mismatch between the line impedance and the load impedance. The initial spike you are seeing at the start of the source pulse would appear to be from a discontinuity closer to the source. Is the source impedance 100 ohms?

 

But, the periodic wave could be experiencing reflections from the previous wave. The period is ~6ns, so that would work out.

 

Make sure your probes are working properly and the input is set for DC (not AC).

 

But, the periodic wave could be experiencing reflections from the previous wave. The period is ~6ns, so that would work out.

There are no reflections if the load impedance matches the trace transmission-line impedance.

 

There are no reflections if the load impedance matches the trace transmission-line impedance.

I agree, not that there is any need to agree with established facts

 

It occurs to me that one way to see if this is reflections is to capture the very first wave with your scope. If it is reflections you see, the very first wave should look very different from the others.

 

It occurs to me that one way to see if this is reflections is to capture the very first wave with your scope. If it is reflections you see, the very first wave should look very different from the others.

If you can convert the waveform to a single long pulse than it's easy to see any reflections.

 

I agree, not that there is any need to agree with established facts

Many of the things talked about in these forums are "established facts". I mentioned that particular fact because the op appeared to be concerned about why he didn't see reflections as he expected.

 

Many of the things talked about in these forums are "established facts". I mentioned that particular fact because the op appeared to be concerned about why he didn't see reflections as he expected.

Isn't it typical for someone to ask a question, and then just leave it up to us to debate

 

Isn't it typical for someone to ask a question, and then just leave it up to us to debate

I though that's what we are doing.

 

I agree, not that there is any need to agree with established facts

Can you imagine how much effort would be spared by the over-unity crowd if folks could just accept the laws of thermodynamics? Challenging dogma can be heroic (Galileo, for example), but there's a line between heroism and stupidity. I guess the line is more clearly drawn to some than others.

[edit] In case it's not clear, I'm not referring to the current topic at all, only the comment about agreeing with facts.

 

It occurs to me that one way to see if this is reflections is to capture the very first wave with your scope. If it is reflections you see, the very first wave should look very different from the others.

Good suggestion. I have attached this trace. So there are 2 new traces I have posted:

1. pcie_refclk_first_edge.jpg - Same trace as original (i.e. very long 19") but now captured on first edge (I can't control it to do a single pulse and observe reflections)
2. pcie_refclk_first_edge_2ndclk.jpg - Same device, different output (i.e. exact same signal, just different output buffer), shorter trace, different receiver of the signal (with a routing constrained impedance mismatch that makes the location of the reflection makes sense to me)

Firstly, why isn't the "reflection" observed in pcie_refclk_first_edge_2ndclk.jpg superimposed to 'increase' the signal at the driver first? I always thought the reflection should be of same polarity and thus superimpose itself to increase for the first reflection cycle. I guess in the case of differential signals the reflection may not be balanced so I can sort of explain that one.

Interesting that in new image pcie_refclk_first_edge, the trace 'appears' not to go negative at first (but the amplitude begs to differ, as ~700mV is the differential voltage, so the ~1.4V swing seen on the first going edge implies full range) on it's first edge but then does swing negative thereafter (Not sure if I should ignore this fact.... somehow I think it's a vital clue). NOTE: Obviously not AC coupled given long holdup at first edge and comparing to the 2ndclk.jpg trace, something is suspicious and the pcie_refclk_first_edge_2ndclk.jpg makes more sense to me.

I'm starting to suspect the receiver at the end of the 19" trace might be up to some funny business as the receiver in the pcie_refclk_first_edge_2ndclk.jpg is a different device and has 100 Ohm internal termination (the reflection seen is due to a routing constraint mismatch of impedance).

Any insight is much obliged.

 

I think I finally have some insight. Below are two simulations of a idealized loss-less 100Ω transmission line with a 3ns delay (about a 19" length). As you can see the idealized traces resemble your two traces with a 100Ω source and using a 50Ω load and a 300Ω load. Not sure if that is a reasonable approximation of your circuit but it is an interesting similarity between the sim traces and your circuit traces.

What appears to be happening is that the load reflection from the leading edge arrives back at the source end in 6ns. This is 1ns after the trailing edge so you get about a 1ns time with no reflection at the start of the next waveform edge and then the rest of the trace includes the reflection.

I believe that makes sense if you think about it.

 

I think I finally have some insight. Below are two simulations of a idealized loss-less 100Ω transmission line with a 3ns delay (about a 19" length). As you can see the idealized traces resemble your two traces with a 100Ω source and using a 50Ω load and a 300Ω load. Not sure if that is a reasonable approximation of your circuit but it is an interesting similarity between the sim traces and your circuit traces.

What appears to be happening is that the load reflection from the leading edge arrives back at the source end in 6ns. This is 1ns after the trailing edge so you get about a 1ns time with no reflection at the start of the next waveform edge and then the rest of the trace includes the reflection.

I believe that makes sense if you think about it.

View attachment 68665 View attachment 68666

Thanks for that Crutschow,

I agree the reflections and timing do add up and make sense to an 'unterminated' load, which for HSCL clock drivers (PCIe style REFCLK) using no termination is actually normal. So I can imagine that for the receiver, there is no internal termination and nor do they call for it (Intel device), however they normally do allow people to run traces as long as I am, so I'm going to throw some termination on it tomorrow and see how it looks.

The one thing that still has me at a bit of a loss is the 'offset' in the first trace, which disappears 'after' the first instance of a transition. This is NOT observed for the second trace (same equipment, same board, same driver, different receiver). Maybe I'll have to ignore this anomaly and just focus on the reflections for now then!

 

Good suggestion. I have attached this trace. So there are 2 new traces I have posted:

1. pcie_refclk_first_edge.jpg - Same trace as original (i.e. very long 19") but now captured on first edge (I can't control it to do a single pulse and observe reflections)

This appears to confirm what we talked about earlier, that reflections from the previous wave interferes with the incident wave in a destructive manner. The fact that the first pulse is unmolested confirms this.

2. pcie_refclk_first_edge_2ndclk.jpg - Same device, different output (i.e. exact same signal, just different output buffer), shorter trace, different receiver of the signal (with a routing constrained impedance mismatch that makes the location of the reflection makes sense to me)

Firstly, why isn't the "reflection" observed in pcie_refclk_first_edge_2ndclk.jpg superimposed to 'increase' the signal at the driver first? I always thought the reflection should be of same polarity and thus superimpose itself to increase for the first reflection cycle. I guess in the case of differential signals the reflection may not be balanced so I can sort of explain that one.

Why do you think the reflection doesn't increase the signal at the driver? I see the pulse beginning to settle at a level ~1/2 full output, but then swinging to full output when the reflected wave hits. Note that if the load impedance is lower than the line impedance, then reflected wave will be subtractive from the incident wave, and visa-versa.

Interesting that in new image pcie_refclk_first_edge, the trace 'appears' not to go negative at first (but the amplitude begs to differ, as ~700mV is the differential voltage, so the ~1.4V swing seen on the first going edge implies full range) on it's first edge but then does swing negative thereafter (Not sure if I should ignore this fact.... somehow I think it's a vital clue).

If the driver has less impedance than the line, the signal will swing more towards full output. If you had a short transmission line as in the other experiment, the output is likely to go significantly higher than full output, but because the driver changes before the reflected wave arrives, it does not.

I'm starting to suspect the receiver at the end of the 19" trace might be up to some funny business as the receiver in the pcie_refclk_first_edge_2ndclk.jpg is a different device and has 100 Ohm internal termination (the reflection seen is due to a routing constraint mismatch of impedance).

Looks normal to me.

 

Thanks for all the responses everyone.

So today I snuck a tiny 100R resistor onto the two vias at the end of trace run and captured this.

Summary: Reflections explain everything. Still a bit fuzzy on the 'offset' observed at first edge but it's gone now so must have been a scope artifact of the differential probe or some such.