My top module has 3 signals
(clk,rst : Inputs
Display : output)
I'm trying to instantiate another module which also has the same 3 signals.
In my top module i used display as a "reg" for calculation purposes.
When i try to instantiate i get an error saying " output or inout port display must be connected to a structural net.
So i changed Display to a net.
Now i get an error saying "left hand side must be of variable data type"
I also tries using a temporary variable to circumvent this problem but keep getting the same error
"left hand side must be of variable data type"
What do i do..

 

Instantiating???
instantiate???

 

First, state that this is Verilog, so that people can do a little research to help you.

Second, post your Verilog do that we may look at it and point out problems.

Third, you assign a flip flop (reg) while in an always statement. It sounds like you left the assignment as the non blocking assignment when, as using a wire, the assignment should be the blocking assignment outside of the always. A wire must be defined for all possible conditions.

 

Instantiating???
instantiate???

Hmm, apparently it's an actual word. News to me

http://verilog.renerta.com/mobile/source/vrg00027.htm