# Relationship between frequency and samples rate of converters

Discussion in 'General Electronics Chat' started by new2circuits, Apr 27, 2009.

1. ### new2circuits Thread Starter Member

Apr 22, 2009
21
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HI : I was wondering if anyone could help me understand the relationship between the frequency and sample rate of a converter ?
To make the exmaple concrete, let's use an adc with the following specs:

8 bit resolution
200 kSPS
3.2MHZ.

Also, is there any rules that need to be adhered to concerning these values ?

From what I've gathered, the sampling rate of the converter has to be atleast TWICE as fast as the incoming signal frequency.

I"m trying to put this all together, but I"m confusing myself.

Any help is appreciated.

thanks

2. ### StayatHomeElectronics Well-Known Member

Sep 25, 2008
864
40
8 bit resolution means you get 256 discrete steps (00000000 - 11111111) between 0 and Vref, or -Vref and Vref, as defined for the particular part.

The 200 kSPS (kilo samples per second) is the sample rate of the converter. That means you can get up to 200000 data points from your input every second. That is the maximum rate for the part.

The 3.2MHz may be the clock frequency that you have to send to the part in order to get the 200 kSPS sample rate. Depending on the number of bits of resolution and the type of converter you are using, a single conversion takes more than one clock cycles to complete. Check the data sheet to see if that makes sense. If it is totally off base then let me know what part you are considering so I can review the data sheet as well.

You are correct in saying the sample rate of the converter has to be at least twice as fast as the incoming signal frequency. That allows you to theoretically reproduce the signal. More samples are often needed depending on the application or to make a visually appealling reproduction of the signal.

Apr 22, 2009
21
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4. ### StayatHomeElectronics Well-Known Member

Sep 25, 2008
864
40
If you look at page 9 of the data sheet you can see that the maximum frequency of the input clock sclk is f(sclk)(max) = 3.4 MHz.

Just below that it shows the time for a conversion t(convert) = 16 * t(sclk), 12 * t(sclk), or 10 * t(sclk) for different parts in the series. t(sclk) = 1 / f(sclk).

There is a timing diagram on page 10.

5. ### new2circuits Thread Starter Member

Apr 22, 2009
21
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HI : So if I understand this correctly, the system clock (sclk) is the frequency required in order to perform the sampling at the rate on the data sheet, again depending on architecture of the adc.

So the relationship that exists between the internal system clock and the sample rate is not standard for all types of architectures, but differs depending on adc architecture, correct ?

Also, the adc can only accept incoming signals up to 100kHZ (keeping Nyquist in mind) for this particular device with a 200kSPS sampling rate, correct ?

Thanks

6. ### StayatHomeElectronics Well-Known Member

Sep 25, 2008
864
40
That is all correct.

7. ### new2circuits Thread Starter Member

Apr 22, 2009
21
0
Great. Thanks.

8. ### StayatHomeElectronics Well-Known Member

Sep 25, 2008
864
40
You're most welcome.