Hi,
Is there any difference in the architecture of register file and standard sram apart from dedicated read/write ports in rf ?(would be great if someone could suggest any helpful links on register file )

 

Each architecture is going to be its own critter. That goes for CPU architectures as well as memory architectures. So you need to focus the discussion on specific architectures.

 

There is tremendous differences in the architecure between a register file and regular memory. Both can be accessed in the same way, logically speaking. Can you restate your question more specifically?

 

Each architecture is going to be its own critter. That goes for CPU architectures as well as memory architectures. So you need to focus the discussion on specific architectures.

I'm sorry was talking about the difference in memory architectures

There is tremendous differences in the architecure between a register file and regular memory. Both can be accessed in the same way, logically speaking. Can you restate your question more specifically?

I'm concerned with the difference in physical architecture of register file sram and a standard sram (which includes the decoder architecture, precharge and sense amplifier circuits).Though i know the read/write operation at gate-level or transistor-level in an sram, not sure if its the same or different in register file(knowing the rf architecture would probably help me understand).Thank you

 

The details of the architecture would depend on the particular processor. Register file memory isn't SRAM based, rather an integrated fast access memory created from logic elements integrated into the processor fabric. It doesn't require precharge and such because it is fast and tightly coupled. Beyond that, I won't be much more help to your understanding. You just have to study a particular processor architecture.