Register Clock Gating

Discussion in 'General Electronics Chat' started by Dritech, Mar 8, 2015.

  1. Dritech

    Thread Starter Well-Known Member

    Sep 21, 2011
    756
    5
    Hi all,
    I was reading the article in the link below, where it says:

    "Because the D-type flip-flop does not have a hold mode and will always cause the copying of its D inputs to the Q outputs on every clock pulse, we gate the clock (not nice) to allow conditional load of the register."

    Why is it 'not nice' to use such layout?

    http://faculty.kfupm.edu.sa/coe/ashraf/RichFilesTeaching/COE022_200/Chapter 5.htm

    Thanks in advance.
     
  2. Hypatia's Protege

    Distinguished Member

    Mar 1, 2015
    2,800
    1,237
    Asynchronous gating of the CP may cause unexpected operation at certain 'junctures'.
    Then, too, it is less than 'elegant' ;)

    Should you insist upon this method, you are best advised to implement a gating circuit that prevents -- but can neither cause nor be asserted during -- a clock transition...

    Best Regards
    HP
     
    Last edited: Mar 8, 2015
  3. Papabravo

    Expert

    Feb 24, 2006
    10,152
    1,794
    The whole idea of a synchronous system is that all the registers are updated at the same time, on the clock edge. Any gating delay will cause that register's output to change later than all the other ungated registers.
     
  4. crutschow

    Expert

    Mar 14, 2008
    13,042
    3,243
    If the clock happens to be asynchronously gated at the rising edge of the clock then you many get a very short clock pulse (glitch) at the gate output which may or may not clock the register (for a positive edge-triggered FF).

    The proper way to gate a clock is to use another flip-flop to control the gate. The gate control would go to the D input and an inverted clock to the FF's clock input. The reason for the inverted clock is so the gate transition occurs at the following edge of the clock and thus won't cause any glitches on the rising (sensitive) edge.
     
    Hypatia's Protege likes this.
  5. Dritech

    Thread Starter Well-Known Member

    Sep 21, 2011
    756
    5
    Thanks for the replies.

    @Papabravo, but the dating circuit is common for all registers, no? So a delay of lets say 1ns will be common to all registers.
     
  6. WBahn

    Moderator

    Mar 31, 2012
    17,768
    4,802
    The description appears to be talking about gating the clocks to individual registers when those registers need to be held. If ALL of the registers always need to be held or updated at the same time, then what's the point of gating a clock as opposed to just using a clock at the right frequency?

    Any time that you have an edge-sensitive circuit you have to pay very careful attention to race conditions and timing hazards. These are not the easiest things to deal with since they often involve layout-specific influences such as trace routing. So it is best to design your logic to be fully synchronous wherever possible. There ARE advantages to asynchronous designs, namely speed, power, and gate count, but the additional significant cost of good design and verification have to be weighed against them.
     
    Hypatia's Protege and Dritech like this.
  7. Papabravo

    Expert

    Feb 24, 2006
    10,152
    1,794
    BTW, the cannonical way to do this, especially inside an FPGA, is to use a 2 input multiplexer on the D input to route either the Q output or the present input to the D input. Problem solved and no messing with the clocks.
     
    Hypatia's Protege likes this.
Loading...