Hey guys, i am just a little confused with the opeation of a JK latch (or flip-flop for that matter.) We were given a nand gate implementation (please see attached file) ages ago and i am trying to study the thing again but cant see how the latch is stable in this condition: Say for example, the enable input if high (in the picture i attached, i forgot to add in the vcc for the enable input but assume its there and its high ;-) anyhoo) and both J and K are both high. Also, the asynchronous preset is low so as to preset the device and the asynchrnonous clear is high. So when this happens, the Q output is high which feeds back to the K input. As said, K is high and so is enable so if Q is also high, this nand gate should go low, making Qbar high.(All the while the asynchrnonous preset input is still left on low) Am i right in saying that the Jk latch is unstable like this so its needs to be in a master-slave configuration or use a level trigger device in tandem with it? If this is correct, does the level trigger device have to be made such that the enable's high duration is very short so the circuit wont oscillate?
All the rest of the circuits states i am happy with i think.
Thanks!
All the rest of the circuits states i am happy with i think.
Thanks!
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