Regarding the truth table of a JK latch

Discussion in 'General Electronics Chat' started by mentaaal, Apr 22, 2008.

  1. mentaaal

    Thread Starter Senior Member

    Oct 17, 2005
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    Hey guys, i am just a little confused with the opeation of a JK latch (or flip-flop for that matter.) We were given a nand gate implementation (please see attached file) ages ago and i am trying to study the thing again but cant see how the latch is stable in this condition: Say for example, the enable input if high (in the picture i attached, i forgot to add in the vcc for the enable input but assume its there and its high ;-) anyhoo) and both J and K are both high. Also, the asynchronous preset is low so as to preset the device and the asynchrnonous clear is high. So when this happens, the Q output is high which feeds back to the K input. As said, K is high and so is enable so if Q is also high, this nand gate should go low, making Qbar high.(All the while the asynchrnonous preset input is still left on low) Am i right in saying that the Jk latch is unstable like this so its needs to be in a master-slave configuration or use a level trigger device in tandem with it? If this is correct, does the level trigger device have to be made such that the enable's high duration is very short so the circuit wont oscillate?

    All the rest of the circuits states i am happy with i think.

    Thanks!
     
  2. mentaaal

    Thread Starter Senior Member

    Oct 17, 2005
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    Oh yeah one more question, i did this in orcad and tried to simulate it but it wouldnt simulate... i am just gettting flat green lines for the output even though i have set the digstim inputs properly as can be seen in the attached pic. (I am aware that i dont have an enable input in the circuit but i have since stuck it in and it still doesnt make a difference.)

    I am finding that running simulations with orcad is very much hit and miss. I would do a circuit and it would work and if i tried another another time it wouldnt work.. GRRRRRRR
     
  3. Caveman

    Active Member

    Apr 15, 2008
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    Why do you think it is metastable?
     
  4. mentaaal

    Thread Starter Senior Member

    Oct 17, 2005
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    Well i am probably wrong about this but i just want to know where i am going wrong. As said above, i think that when the preset is low such that the Q output will be high, this will feedbad to the K input NAND gate. If, at this time, the k input happens to be high as well as the enable input, then all the inputs to the K input NAND gate will be high so the output of it will be low so then Qbar will also be high which isnt allowed...... ?????am i missing something here?
     
  5. jericko

    Member

    Apr 21, 2008
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  6. jericko

    Member

    Apr 21, 2008
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    set j,k, preset,clear to one and clock it, at the negative of the clock signal it will toggel. this will cause your oscillations if im not mistaken.
     
  7. mentaaal

    Thread Starter Senior Member

    Oct 17, 2005
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    According to my teacher, i am right, and its called the hazard condition which needs to be avoided, by using an edge triggered device or a master-slave configuration. (just found out today)

    thanks for the help though you guys
     
  8. nomurphy

    AAC Fanatic!

    Aug 8, 2005
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    You may also want to talk to your teacher, or look up the subject, about clock hardening which is related to this issue and is often overlooked by designers.
     
  9. Dave

    Retired Moderator

    Nov 17, 2003
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    What is "clock hardening"? I've never come across that term.

    Dave
     
  10. nomurphy

    AAC Fanatic!

    Aug 8, 2005
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    Various methodologies such as "double buffering" have been developed to overcome output glitches (a big issue with clocks for synchronous designs), caused by metastability and race conditions inherent in flip-flops / counters.
     
  11. Dave

    Retired Moderator

    Nov 17, 2003
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    Thanks. Never heard of it referred to by the term "clock hardening".

    Dave
     
  12. Caveman

    Active Member

    Apr 15, 2008
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    Doesn't come up on google either. Weird.
     
  13. Dave

    Retired Moderator

    Nov 17, 2003
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    That's why I was a touch confused. I tried looking through the IEEE Explore archive to see if there were any papers referring to it, and that also turned up blanks.

    Will keep my eye out in future.

    Dave
     
  14. JoeJester

    AAC Fanatic!

    Apr 26, 2005
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    very little, besides this thread, had come up at google
     
  15. Papabravo

    Expert

    Feb 24, 2006
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    This problem can be observed with a test setup that can move changes on the JK inputs relative to the clock edge. As the setup and hold requirements of the flip-flop implementation are violated, all manner of metastable behaviour can be observed including, but not limted to 'runt' pulses, invalid states, long recovery times, and so forth.

    As likely as such violations are on the inputs to syncronizers it really is a wonder that stuff seems to work as well as it does.

    Her is the first accessible non-IEEE, non-ACM web page on metastable behavior that I could find. I knda like the three ball diagram. Reminds of of my youth when I worked in a pawn shop.

    http://www.asic-world.com/tidbits/metastablity.html
     
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