Hi again!

I have made some measurements with the scope (with the standard cable that I use, the shielded). I attach here some pictures.

• 
  FIGURE 0 shows the rise time of SCLK measured at the main PCB, when the remote sensor is connected (it was found 170ns)

• 
  FIGURE 1 shows the rise time of SCLK measured at the remote PCB, at the sensor (it was found to be 140ns)

• 
  FIGURE 2 shows the rise time of SCLK when the remote sensor is not connected (it was found to be 33ns)

Is it possible that this increase to the rise time of the clock can create the inability of the processor to reach the SPI devices? I cannot understand (in fact I don't know it at all) why the increase of the rise time of this signal can lead to the device being inaccessible.

Is there any way to solve this issue of the rise time (without the need to use a buffer)? Which else signal should I measure with the scope?

nick

 

The transmit driver is clearly driving a capacitive load with two components.

1. The distributed capacitance of the cable
2. The pin to ground capacitance of the sensor.

It would also be helpful to look at the discharge waveform. With a push-pull output stage the rise and fall times should be similar. With any other arrangement the distributed capacitance of the cable could lead to a very long discharge time.

With a CMOS output stage that can source as much current as it can sink this is usually not a big problem. With an asymmetrical output stage, such as a TTL totem pole, that can sink more than it can source or vice versa the difference in rise and fall time will astound you.

Find yourself a table online that gives the resistance of 26 AWG and compute the IR drop along your cables for the forward and reverse path based on the datasheet values for sink and source currents at different voltage drops. Remember that even a CMOS driver will drop it's output high voltage as you try to force it to source more current.

Another thing to try is one of the other SPI modes (there are 4 of them altogether) if possible. Usually the peripheral chooses one of the modes and the master adapts.

If all else fails then do an experiment with CMOS drivers and receivers that have LVTTL thresholds. This is important in systems with different VCC values. The way this works is that the thresholds are independent of VCC. In a normal CMOS part the threshold is set at VCC/2 which is not what you want. What you want is Vol at 0.4 to 0.8 volts and Voh at 2.0 Volts. The VCC for each of the buffers should come from the transmitting side since the inputs are capable of withstanding voltages in excess of VCC. You can do this with SPI. It is much more difficult with I2C because of the requirement for bi-directionality.

 

Can you put up a shot of the signals when there is only 1 foot of wire between the two devices, and working at the same frequency?

All wire will have a capacitive load, you may need to go to 5V logic for the distances you are working with. If I read the scope right, you are at 3.3v?