read input file in vhdl !

Discussion in 'Embedded Systems and Microcontrollers' started by charko, May 19, 2010.

  1. charko

    Thread Starter New Member

    Apr 27, 2010
    11
    0
    Helle everybody!

    I want to test this vhdl code for read input file and i don't know how i can do that . Please can you tell me if someone have any idea .
    I will be grateful for your help .

    Charko!
    ------------------vhdl code for input file------------------------


    library ieee;
    use std.textio.all;

    entity lecture is end;

    architecture arch of lecture is
    begin
    read_input_file : process
    variable inline: line;
    variable character_variable:character;
    variable fin_de_ligne: boolean ;
    file myfile: text is "data.txt";
    begin
    while not endfile(myfile ) loop -- tant qu'on a pas la fin du fichier on fait une boucle
    readline(myfile,inline); -- on lit tout le fichier
    read(inline,character_variable,fin_de_ligne);
    --end_of_line is EOLN Boolean flag
    while fin_de_ligne loop -- tant qu'on atteint la fin du fichier
    read(inline,character_variable,fin_de_ligne);
    end loop;
    end loop;
    wait; -- ne rien faire lorsque c'est fini
    end process read_input_file;
    end arch;
     
  2. kingdano

    Member

    Apr 14, 2010
    377
    19
    generally the only way to test VHDL/Verilog code is to write code to test it using ModelSim or similar

    you can try to test with hardware or in an actual system - but you may miss bugs/glitches.

    as far as details on how to do that in ModelSim i cant be any help unfortunately.
     
  3. charko

    Thread Starter New Member

    Apr 27, 2010
    11
    0

    Thank you for your response.
     
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