i have exam tomorrow.urgent help required
the problem is
draw the logic diagram of a 4 bit register with 4 D flip flops and four 4 to 1 multiplexers with mode selection inputs s1 and s0.The register operates according to the following function table.
S1 S0 Register operations
0 0 No change
0 1 Complement the four outputs
1 0 Clear register to 0(synchronous with the clock)
1 1 Load parallel data
the problem is
draw the logic diagram of a 4 bit register with 4 D flip flops and four 4 to 1 multiplexers with mode selection inputs s1 and s0.The register operates according to the following function table.
S1 S0 Register operations
0 0 No change
0 1 Complement the four outputs
1 0 Clear register to 0(synchronous with the clock)
1 1 Load parallel data