RAM DESIGN

Kermit2

Joined Feb 5, 2010
4,162
You should place them parallel with shared address bus lines but each with its own independent read and right line.
 

WBahn

Joined Mar 31, 2012
30,088
You should place them parallel with shared address bus lines but each with its own independent read and right line.
But they can share the left lines? :D

Interesting coincidence in that I made the same mistake last week and I think I've seen at least two other folks make it in that same time frame. Of course, it's an easy typo to make and we all have made it many times.
 

Papabravo

Joined Feb 24, 2006
21,228
You can only read and write to an enabled chip. Each address will select four of the sixteen total chips to read from and write to.
 
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