# Quickest way to make logic gate output last for a few seconds?

Discussion in 'The Projects Forum' started by Orbitingful, Jan 27, 2016.

1. ### Orbitingful Thread Starter Member

Oct 31, 2015
32
1
What is the quickest way to make the out of an AND gate last for 1 second only? In other words, for the output to be high for only 1 second. Is there a quick way to do this - I have considered using a monostable. Below is a schematic of an implementation of this idea with a XOR gate.

I need a similar configuration with an AND gate.

Last edited: Jan 27, 2016
2. ### Papabravo Expert

Feb 24, 2006
10,338
1,850
Well it kind of depends on how accurate you want the trailing edge to be. A monostable or one-shot will do the job but the time will vary from one instance to the next. The accurate way to do it is with a Finite State Machine and an accurate clock signal.

3. ### WBahn Moderator

Mar 31, 2012
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You need to be clear on what you mean by making the output last for one second. Do you mean that when the output goes HI it stays HI for one second and returns LO even though all of the inputs are still HI?

The approach shown above works to get narrow pulses. Given the speed of even slow logic families, you would need millions of inverters to get to a one second pulse. It also has very poor accuracy.

Why have you only considered a monostable circuit? What is it about it that caused you to reject it?

What is important in this circuit? Accuracy? Precision?

4. ### Orbitingful Thread Starter Member

Oct 31, 2015
32
1
I don't really care how long the pulse is - less than one second is fine - I need it to be very short. Yes I want the pulse to go from high to low regardless of what the inputs are.

5. ### WBahn Moderator

Mar 31, 2012
18,079
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What is "very short"? There is a HUGE difference between generating a pulse that is 0.5 microseconds and one that is 0.5 seconds.

If you don't really care how long the pulse is, then why is a monostable not acceptable?

6. ### WBahn Moderator

Mar 31, 2012
18,079
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How many different signals are being ANDed together here? What should happen if one of those signals goes LO before the pulse has expired? Should the output continue to remain HI for the rest of it's normal duration, or should it go immediately LO?

7. ### WBahn Moderator

Mar 31, 2012
18,079
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Have you looked at just replacing the XOR with an AND and just using a single NOT gate?

8. ### crutschow Expert

Mar 14, 2008
13,469
3,356
Your XOR circuit will give two output pulses, one on the leading edge and one on the trailing edge of the input signal.
Is that what you want?
Or do you just want a pulse on the leading edge?

9. ### AnalogKid Distinguished Member

Aug 1, 2013
4,677
1,294
The quickest way is to think about what you really need, then think about what a professional circuit designer might need to know to come up with a circuit that will work *in you application*, then ask a detailed question that includes things like the available power supply, all of the input signals, the output signal voltage and current requirements, what the circuit is driving, where the inputs are coming from, what the range of acceptable pulse widths is, which input conditions trigger the output, and which conditions can be ignored, what parts or logic families you have access to, and what your assembly skill set is. A truth table would be nice.

ak

panic mode likes this.
10. ### dl324 Distinguished Member

Mar 30, 2015
3,375
651
Your requirements are a bit vague.

Here's a CMOS AND gate that will give a positive pulse on the rising edge of the input. Select R and C values for the pulse duration you desire.

11. ### WBahn Moderator

Mar 31, 2012
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That circuit really needs a protection diode to keep Pin 2 from going more than a diode drop below GND on the negative-going edges.

12. ### dl324 Distinguished Member

Mar 30, 2015
3,375
651
The standard input protection takes care of that.

13. ### Alec_t AAC Fanatic!

Sep 17, 2013
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But the standard input protection can handle only small currents and energy. If C1 is a fat cap (which it would need to be for lengthy time constants) it might pass excessive current or store excessive energy. A series resistor to the gate input would limit current.

14. ### dl324 Distinguished Member

Mar 30, 2015
3,375
651
OP asked for a very short pulse, so it won't be a problem. Variations of the circuit appear in an RCA app note.

15. ### shortbus AAC Fanatic!

Sep 30, 2009
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Glad this came up, saves me from making a thread. In the circuit shown, how does the cap pass a positive/high voltage to the 'and gate'? Was under the assumption that caps don't pass DC through them. Since C1 is connected through R1 to ground/common, how does a positive/high get on terminal 2 of the gate?

16. ### hp1729 Well-Known Member

Nov 23, 2015
2,071
230
The positive edge of the signal is what passes through the capacitor.

shortbus likes this.
17. ### Orbitingful Thread Starter Member

Oct 31, 2015
32
1
When I use the monostable, if the trigger is a falling edge, and stays low, the output of the monostable stays high. How do I get the monostable to go back to 0v, despite the trigger staying low continuously?

Thanks.

18. ### Alec_t AAC Fanatic!

Sep 17, 2013
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You connect the gate output to pin 2 of the 555 via a capacitor (say 10nF) and connect pin 2 to the +ve rail via a pull-up resistor (say 10k).

19. ### Orbitingful Thread Starter Member

Oct 31, 2015
32
1
That causes the output to remain high all the time. It doesn't go low at all. Could you provide a schematic?

Last edited: Jan 28, 2016
20. ### Orbitingful Thread Starter Member

Oct 31, 2015
32
1
I want it so when all the inputs of the nor gate are low, the output of the monostable is high then low.