Questions about oscillators

Discussion in 'Wireless & RF Design' started by Adarx, May 24, 2014.

  1. Adarx

    Thread Starter New Member

    May 24, 2014
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    First of all, hello to all ! I just registered on this forum after lurking for a while. I've been interested in electronics for quite awhile but only got to really study it in detail after I joined my local Ham Radio club. I'm currently using the 2014 ARRL Handbook to teach myself radio technique, and I'm loving it! But there a few things I just can't wrap my head around :/

    One of these things is oscillators. The 2 circuits in the attachment are taken directly from the handbook.

    I don't totally understand how A) works. The way I see it, some noise will make its way into the LC tank circuit. The LC circuit will filter it, and at the beginning I will have a very small amplitude sine wave of frequency 1/(2∏*√LC)) at the entrance of my amplifier. The amplifier which has unity gain will produce the same signal and inject it into the LC circuit. So now Vtank = V1. If I understand correctly, I'm constantly adding more energy into the LC circuit, thus raising the amplitude of my sine wave. At one point though won't the amplitude become so great that the amplifier saturates and I'd end up with a square-like signal at V1? And wouldn't injecting V1 anywhere in the tank circuit work aswell?

    B) is also a mystery to me. Part of the reason is because I don't really "get" A) :p But also, I understand we have an RF choke to prevent the AC signal to go to ground instead of our output, but why do we have an RF bypass at the Drain?

    Thanks in advance for taking the time to help :)!
     
  2. t_n_k

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    Mar 6, 2009
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    In the first example there are no dynamic limits on the growth of voltage amplitude. So it is true the observed stored energy could grow indefinitely as there is no means of amplitude limiting or energy dissipation in the idealized schematic.

    The second more realistic schematic will have dynamic limits as well as bandwidth limitations & energy loss. The drain terminal is RF bypassed as the amplifier is operating in a common drain or voltage follower topology / mode.
     
    Last edited: May 26, 2014
  3. Adarx

    Thread Starter New Member

    May 24, 2014
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    Thanks for answering!

    Could you explain what you mean by dynamic limits? As the voltage goes up will the FET's gain (unity here) drop ?

    I looked up common drain FET amplifiers, and they do indeed have the bypass capacitor at the drain terminal. I just don't understand why?
     
  4. #12

    Expert

    Nov 30, 2010
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    A jfet (and a bipolar transistor) have less gain as the voltage available at the drain (collector) approaches zero. (Yes, the gain decreases.)

    The capacitor at the drain is local to the transistor because wires and circuit board traces have inductance. A capacitor 5 inches away has no chance of being effective at RF frequencies.
     
  5. t_n_k

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    You made a reference to output clipping or squaring up as the amplitude increases. This is true in any real circuit implementation where the amplifying device output is dynamically limited - such as through saturation or cut-off.
     
  6. PRS

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    Aug 24, 2008
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    The amplifier of circuit 2 seems to be a common drain circuit. And in that case it's hard to see how the feedback is getting the required gain (just a little over unity) even if there really is a tie point at the source going back into the tank. (You didn't show one).

    The resistor at the drain is not for gain but for decoupling the power rail from the signal so it isn't corrupted and the signal therefore is sent to other places in the overall circuit where it shouldn't go. The resistor is about 100 ohms while the capacitor associated with it is about .01 or .1 uF and dumps the signal to ground. It's an RC filter.

    The choke at the source just doesn't make sense to me because the resistor by itself sets the dc level at the source and the signal rides the dc level. Check the original drawing and correct it for us, please.
     
    Last edited: May 27, 2014
  7. t_n_k

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    I don't have access to the ARRL handbook cited. The second "practical" circuit may have been transcribed by the OP (Adarx) from the original in the ARRL handbook with an error of omission. I suspect the bottom of the tank circuit should be grounded rather than floating as shown. And as PRS points out, there should be a tie point for the feedback from the FET source lead. With those changes added to the schematic it should be possible to have sustained oscillation.

    Also the schematic is reminiscent of a Clapp oscillator rather than the simpler Colpitts topology of the first "ideal" circuit. Whilst the two topologies are closely related, it may be worth noting the difference. Perhaps there were other errors in the transcription in the OP's attachment.

    I agree with PRS that the RFC in the source leg probably serves little purpose other than reducing the RF losses in the bias circuit, which is likely of little consequence in the overall design.

    Perhaps the self-biasing form shows how the source RFC can be put to good use - see attached schematic. It could well be the case that this was the actual topology seen by the OP in the ARRL Handbook.

    Finally, it's interesting how few components one actually needs to get a JFET Colpitts running ...

    http://www.edn.com/design/analog/4327634/JFETs-offer-LC-oscillators-with-few-components
     
    Last edited: May 28, 2014
  8. Adarx

    Thread Starter New Member

    May 24, 2014
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    Thanks everyone for you help ! The circuit's a lot clearer to me now.

    I did indeed forget the tie-in point between the source and the tank. I checked the schematic, the RF chocke at the source is there. I thought it simply prevented the signal from "escaping" to ground instead of our output.

    I'm sending the corrected circuit in this attachment, sorry for the misunderstanding.

    One last thing is bugging me though, why do we have C2 ? Wouldn't C3 and C4 be enough, just as the link t_n_k suggested? Thanks for the link by the way, I don't think the ARRL book has the "mathematical" explanation to this oscillator.
     
    Last edited by a moderator: May 29, 2014
  9. PRS

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    Aug 24, 2008
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    I believe C2 is just a decoupling capacitor. It has nothing to do with the circuit's oscillating frequency. And as for that choke to ground, I still don't see it.
     
  10. t_n_k

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    Last edited: May 28, 2014
  11. vk6zgo

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    Jul 21, 2012
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    The choke is so that the resistor doesn't form any part of the source load at RF.
     
  12. PRS

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    Aug 24, 2008
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    I don't understand this. As I see it, the choke allows the resistor to bias the source. But then it adds resistance as the real part of XL such that the tank AC is looking at Rs + XL, which is somehow stimulating the gain.

    I am intuitively thinking that the choke is somehow creating a gain at the source that is larger than it would be with just Rs. For Rs by itself cannot give unity gain, which is what is the least amount called for to make an oscillator.
     
  13. t_n_k

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    Hi Paul,
    I believe you are overlooking the role of the capacitors in the circuit behavior. Putting aside the role of C2 for the moment, it is possible to show for ideal circuit elements that the capacitors C2 & C3 (as shown in the OP's corrected schematic) when used in a simple Colpitt's arrangement provide a 'transformer' gain of (C3+C4)/C3. Hence one does not need unity gain from the source follower configuration - i.e. from gate to source. Rather the follower only needs to provide something more than C3/(C3+C4) to give the necessary overall loop gain of unity or that value necessary to ensure sustained oscillation - having regard to losses and loading effects.

    With respect to C2, I believe this is indicative of the Seiler configuration I referenced in post #10. C2 is made just large enough to ensure sustained oscillation. It serves to isolate the tank L & C1 from the capacitive transforming network. So the oscillation frequency is notionally related to the values of L & C1 alone. Although there will always be some additional parallel capacitance to be considered due to the combined effect of C2, C3 & C4.
     
    Last edited: May 29, 2014
  14. vk6zgo

    Active Member

    Jul 21, 2012
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    Your intuition is leading you astray.

    Something like what you describe is used in discrete Video Amplifiers,where an Inductor is added in series with the Collector resistor of a Common Emitter stage.
    This is known as "HF peaking"----the Reactance of the inductor becomes a more important part of the load Impedance as frequency increases.

    RF Amplifiers & Oscillators are different!
    In the circuit being discussed in this thread,the Source load is the LC resonant circuit.
    Neither XL or Rs are involved in setting the stage gain,as the value of XL is so high at the operating frequency,it approaches an open circuit for RF.

    All Rs does is provide part of the Gate bias for the FET,& provide a connection to ground for the DC component of the Source current.
     
    Last edited: May 30, 2014
  15. PRS

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    Aug 24, 2008
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    I do believe you're right. Thanks tnk.
     
  16. PRS

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    Intuition isn't worth much, is it? Thanks for setting it straight.
     
  17. KL7AJ

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    Nov 4, 2008
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    Although the op amp in Fig 1 has unity gain, the tank circuit does not! The "tap" point is lower impedance than the TOP of the circuit, so there will be voltage gain because of the Q of the circuit.

    Figure 1 is a very standard Colpitts oscillator. It also uses the Q of the tank to increase the voltage to the gate.
     
  18. BR-549

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    Sep 22, 2013
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    Hello Adarx, the first daigram is just a pictorial showing an amp with feedback. The second diagram is perfect as your first oscillator. Disconnect the top part of C3. Remove C4 from circuit, move it over to the right.....connect C4 to top of rf chock and to ground. Remove fet. Look at L, C1, C2 and Rg(gate resistor) only. Nothing else exist in the universe. Connect scope to top of Rg. Set scope for tank frequency. Find a small value electrolytic cap(5-10uf). Call this cap Ct(test). Now charge this cap to +5V or +9V or +12V or anything at all...just put a charge on it. Using alligator jumpers, connect ground of Ct to bottom of L or C1. While watching scope......momentarily(very quickly) touch the + side of Ct to top of L or C1. Watch the scope. What did you see across Rg? You should see a sine wave of decreasing amplitude, but maintaining frequency. Do it several times and watch it. That's called ringing a tank circuit. Any voltage or current introduced to the tank circuit will start it oscillating. Depending on the configuration and layout of L.......you could take a strong magnate very close to L....and remove magnet very quickly........and ring the circuit too. When oscillating....there is a high AC voltage at the top of tank(+and-20-30 volts and higher). C3 picks or couples a little of that voltage and applies it to the top of Rg. Rg is the load for the tank circuit. Rg has a + and - 1 or 2 volts across it. Remove scope from Rg and attach to top of C4. Install fet. Pwr up board. Shock tank again with Ct. What do you see? It should be a close copy of what you saw across Rg. C4 is the load for the fet. The rf choke is to keep rf from escaping to ground thru the resistor. It keeps the ac output of fet fully impressed across C4. Now move C4 back where is was. Now we are going to pick off a little voltage off of C4 and put it back into tank circuit.....so oscillator doesn't stop. Connect C3. C3 picks a little voltage off of C4 and applies it to Rg and the tank circuit thru C2. Now we can have sustained oscillation. I hope this didn't confuse you. I am assuming a lot of knowledge on your part. If you don't understand something....now's the time to ask. You have to have a good understanding of oscillators. A lot of times you get oscillation when you don't want it. You need to understand what causes it and how to stop it, as well as what makes it. K
     
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