So I have the following CMOS logic circuit
I am pretty sure this is a logical NAND gate, but no 100%. Can someone guide me through a couple steps to get the truth table for this circuit?
Also, I need to find the equations propagation delays Tphl and Tplh for input A. I got the following equation for Tphl of just a logical inverter, but it needs to be modified in some way to fit the above circuit.
Can anyone help me?
I am pretty sure this is a logical NAND gate, but no 100%. Can someone guide me through a couple steps to get the truth table for this circuit?
Also, I need to find the equations propagation delays Tphl and Tplh for input A. I got the following equation for Tphl of just a logical inverter, but it needs to be modified in some way to fit the above circuit.
Can anyone help me?