Question about propagation delays for 3 input CMOS logic gates

Discussion in 'Homework Help' started by hrstar24, Dec 13, 2010.

  1. hrstar24

    Thread Starter Active Member

    Apr 7, 2009
    So I have the following CMOS logic circuit


    I am pretty sure this is a logical NAND gate, but no 100%. Can someone guide me through a couple steps to get the truth table for this circuit?

    Also, I need to find the equations propagation delays Tphl and Tplh for input A. I got the following equation for Tphl of just a logical inverter, but it needs to be modified in some way to fit the above circuit.


    Can anyone help me?
  2. Jony130

    AAC Fanatic!

    Feb 17, 2009
    Well it is quite simple circuit.

    Becaues if we any input will be in LOW state, then output will be in HIGH.
    Thanks to QPA, QPB, QPC
    And LOW output results only if all the inputs are HIGH state.
    Becaues all QNA, QNB and QNC must be "ON" to get low state on the output.
  3. hrstar24

    Thread Starter Active Member

    Apr 7, 2009
    Ah ok thanks for the explanation, can you help me out with the propagation delay problem now? The question asks for the propagation delay equation tphl if the circuit is moved to a single input (A).
  4. hrstar24

    Thread Starter Active Member

    Apr 7, 2009
    bump can anyone help with the propogation delay of the circuit if only a single input (A) is moved?
  5. tyblu


    Nov 29, 2010
    First you have to size the gates of the transistors such that the pull-up network and pull-down network have equal strengths. You can do this with respect to your minimum technology size (smallest is "1"). For this, you'll have to refer to your prof's convention for hole to electron mobility ratio; I've used 1:2 for FETs and I believe 1:5 for GaAs, but have seen many other ratios commonly used.
    hrstar24 likes this.
  6. Georacer


    Nov 25, 2009
    In this particular circuit, and supposing we are using FETs, as tyblu said, we need the Pull Up Network to be twice as fast as the Pull Down Network. So let's say we need the PUN to have a length of 2 and the PDN a length of 1.

    At the PUN the transistors are connected in parallel, so to achieve the total length of 2, we need transistors of length 2.

    At the PDN the transistors are connected in series. The speed of the network is reversely analogous to its transistor lengths. Therefore, each NMOS must have a length of 3, and in total the combined length of the PDN will be 1/3+1/3+1/3=1, which is the desired.