Question about over-capacitance.

Discussion in 'General Electronics Chat' started by alphacat, Jul 14, 2009.

  1. alphacat

    Thread Starter Active Member

    Jun 6, 2009
    186
    0
    Hello.

    I have a problem in my board.
    I was hoping that maybe someone here has already ran into such problem and could give me a clue for the source of this problem.

    In the board there are two ICs - Microcontroller & USB-to-UART Bridge - which are both connected to the same 47 kOhm pull-up resistor that connects to 3.3V.
    The 3.3V comes from a 3.3V regulator that's driven by a 5V USB (the USB connects to a PC).

    The problem is that when I connect the USB to the board, then the two RESET pins reach 3.3V only 200uSec after the VDD reaches 3.3V (The voltage curve of these two pins is just like a capacitor voltage curve).
    That causes every POR (power-up reset) to be recognized in the UC as an HW reset (and thats the problem).

    When I connected each Reset pin to its own pull-up resistor (without connecting the two Reset pins), then the delay has dropped from 200uSec to below 100uSec and the Power-Up-Reset wasnt recognized in the UC as HW-Reset anymore.

    Could you tell me please why connecting the two reset pins causes a 200uSec delay, and disattaching them from each other reduces the delay?

    The reset pin of the USB-to-UART bridge is an open-drain pin, so I dont see how it could add capacitance to the reset pin of the UC.

    Thank you very much guys.
     
  2. studiot

    AAC Fanatic!

    Nov 9, 2007
    5,005
    513
    Are the resets one for each IC or are they both on the same IC?
     
  3. russ_hensel

    Well-Known Member

    Jan 11, 2009
    818
    47
    The two reisistors, if in parallel would have a resistance of about 23K. Try a single resistor for pull up in that range. -- This is without knowing anything about these chips.
     
  4. alphacat

    Thread Starter Active Member

    Jun 6, 2009
    186
    0
    Each IC has its own reset pin.
    In my board, these two reset pins are connected together by a trace, and to the same pull up resistor.

    As I said, I did an experiment where I cut off this trace (that connected the two reset pins) and connected each reset pin to its own pull-up resistor.
     
  5. alphacat

    Thread Starter Active Member

    Jun 6, 2009
    186
    0
    Hello,

    I think that you misunderstood me.
    Originally, the two reset pins are both connected to a single 47k-Ohm pull-up resistor.
    By the way, I also replaced the 47k-Ohm resistor by an 4.7k-Ohm resistor, but each POR was still recognized as HW-Reset in the UC, so it didnt help.

    In my experiment, I firstly cut off the trace that connected the two reset pins, and then I connected each reset pin to its own pull-up resistor, so in this configuration, the two pull-up resistors are not connected in parallel.
     
  6. studiot

    AAC Fanatic!

    Nov 9, 2007
    5,005
    513
    OK well consider that each chip is quite different but both have a ground connection.

    This means that the current path characteristics (capacitance, resistance etc) from ground to the low side of the pull up resistor will be quite different.

    This is the same as if you had connected two different value capacitors together in parallel, grounded one side and connected the other to the pull up resistor. Both caps would not charge at the same rate.

    I expect that if you monitor the separate pull up resistors you will see the same effect.
     
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