Question about logisim and logic

Discussion in 'General Electronics Chat' started by raint, Nov 16, 2013.

  1. raint

    Thread Starter New Member

    Nov 16, 2013
    2
    0
    Hi guys. I am working on a logic diagram and stumbled upon something that I can't understand. I'm adding picture below.

    [​IMG]

    So here is T-FlipFlop, button, AND gate and counter.

    According to my knowledge, counter should update only on every second button click since AND gate gives out rising and falling edge every second time.. however, i get that counter is updated on every button click.. even when output of AND gate stays low.

    Why could that be?
     
  2. crutschow

    Expert

    Mar 14, 2008
    12,993
    3,229
    That circuit has a race condition. It would likely output a short glitch pulse at the AND gate output, equal in length to the propagation delay through the FF, when the input pulse goes high with the FF being triggered for Q to go low.
     
    raint likes this.
  3. raint

    Thread Starter New Member

    Nov 16, 2013
    2
    0
    I understand now. Thank you very much. :)
     
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