PWM frequency divider

Discussion in 'General Electronics Chat' started by DominusDRR, Sep 3, 2009.

  1. DominusDRR

    Thread Starter Member

    May 25, 2009
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    Greetings.

    Is there any way to divide the frequency of a PWM signal and simultaneously also the duty cycle with flips flops and logic gates?

    Thanks.

    Fabián
     
  2. bertus

    Administrator

    Apr 5, 2008
    15,645
    2,344
    Hello,

    When you put a PWM signal into a divider, you will end up with a signal of half the frequency and 50 % duty cycle.

    A possibilty is to take an AND port take the input signal and the divided signal.
    You will get a signal with half the frequency and half teh duty cycle.

    Greetings,
    Bertus
     
  3. DominusDRR

    Thread Starter Member

    May 25, 2009
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    [​IMG]

    Is it correct?
     
  4. Ron H

    AAC Fanatic!

    Apr 14, 2005
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    As bertus said, it will give you half the original duty cycle. That's not what you asked for.
     
  5. DominusDRR

    Thread Starter Member

    May 25, 2009
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    Hello. Thanks for responding. I do not want half, I want double the time in duty cycle
     
    Last edited: Sep 3, 2009
  6. DominusDRR

    Thread Starter Member

    May 25, 2009
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    [​IMG]
    I have this circuit. In IN when the duty cycle is 10% in OUT duty cycle is 95%. When IN the duty cycle is 90%, the duty cycle at OUT is 55%. Responds to the equation 1-t / 2 (where t is the duty cycle in IN in%)

    I need to divide the PWM signal several times (I need to measure the duty cycle of a high frequency signal), but using this circuit the duty cycle changes according to:

    Period __________Duty cycle (%)
    T ______________ t
    2T _____________ 1-t / 2
    4T _____________ 1/2-t/4
    8T _____________ 3/4-t/8
    etc
    Ultimately, the duty cycle variation is so slim that you can not measure.

    Thanks
     
    Last edited: Sep 3, 2009
  7. hgmjr

    Moderator

    Jan 28, 2005
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    It seems to me that one solution would involve converting the PWM signal to its equivalent DC level using an RC filter. You would also need to divide the squarewave by whatever factor you are looking for. You would then need to use the lower frequency squarewave to generate a new ramp the repetition rate of which would be the same as the new lower frequency squarewave. You would then use the recovered DC and the new ramp as inputs to a comparator. The new PWM would be the same as the old PWM only at the slower rate.

    hgmjr
     
  8. DominusDRR

    Thread Starter Member

    May 25, 2009
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    It seems a solution. But it doesn't work in a SPWM signal.

    buscar
     
  9. hgmjr

    Moderator

    Jan 28, 2005
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    So do I take this to mean that you are dealing with a Sinusoidal PWM signal rather than a conventional PWM signal?

    hgmjr
     
  10. Ron H

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    Apr 14, 2005
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    Can you describe in detail what you are trying to do, and why?
     
  11. eblc1388

    Senior Member

    Nov 28, 2008
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    DominusDRR,

    Are you asking the question if a given PWM frequency can be reduced to(1/2, 1/3, 1/4...) by logic gates while keeping the same duty cycle?

    Interesting question albeit I don't know the answer.
     
  12. DominusDRR

    Thread Starter Member

    May 25, 2009
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    Yes. It's a sinusoidal signal that is compared with a triangular wave.
    The sinusoidal signal is 1 MHz and 100 MHz triangular
     
  13. DominusDRR

    Thread Starter Member

    May 25, 2009
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    I'm building a kind of AD converter. I don't want to use a 100MSPS ADC for the following reasons:

    1. The ADC is very expensive.
    2. I use a 40 MIPS microcontroller, so it is very difficult for my microcontroller reaches 100 MSPS ADC.
     
  14. Ron H

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    Apr 14, 2005
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    I don't understand how your 100MHz PWM relates to an ADC. Please provide a block diagram of what you are trying to do.
     
  15. DominusDRR

    Thread Starter Member

    May 25, 2009
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    The variation of duty cycle is proportional to the analog signal. When the duty cycle is zero, implies that the analog signal voltage is zero. When the duty cycle is equal to 100%, the analog signal is at its maximum level. The amplitude of both signals is the same.

    I get different and proportional duty cycles per 10 ns (100MHz).

    :S
     
  16. Ron H

    AAC Fanatic!

    Apr 14, 2005
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    How about a block diagram of the hardware you propose to use?
     
  17. DominusDRR

    Thread Starter Member

    May 25, 2009
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    It's not complicated I want to do. Simply divide the SPWM signal for example up to 32 times, (3.125 MHz). Assuming the duty cicle somehow remains in proportion to the original, I would use the module comparison of my microcontroller to measure the duty cycle time. This time is proportional to the amplitude of my 100 MHz analog signal.
     
  18. Ron H

    AAC Fanatic!

    Apr 14, 2005
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    If you are modulating the duty cycle at 1MHz, how can you get useful information about that modulation if you divide the PWM frequency by 32?
     
  19. DominusDRR

    Thread Starter Member

    May 25, 2009
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    For example assuming that the duty cycle at some point is 10%, this implies that it's 1 ns, by dividing the frequency of some special arrangement of logic gates will be the new frequency of 3,125 MHz or a period of 320 ns. If the duty cycle is kept in proportion, also will be 10%, meaning that it's 32 ns. This time can be measured by my microcontroller.
     
  20. blueroomelectronics

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    Jul 22, 2007
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    Ok I'll ask, what is this for? Are you trying to measure the speed of light?
     
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