Push Pull stage in voltage doubler

Discussion in 'General Electronics Chat' started by cougle, Mar 19, 2013.

  1. cougle

    Thread Starter New Member

    Mar 19, 2013
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    Hi !

    Would someone point out what is the use of complementary transistor pair after the second diode in voltage doubler circuit as shown in circuit?

    Couldn't figure out its purpose here? and simulations give convergence problems.
     
  2. bountyhunter

    Well-Known Member

    Sep 7, 2009
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    That schematic can't be right.
     
  3. cougle

    Thread Starter New Member

    Mar 19, 2013
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    Why can't it be right i.e which connection is false? alternate connection?
     
  4. bountyhunter

    Well-Known Member

    Sep 7, 2009
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    The drive signal coming through D8 goes to the collector of the NPN. That looks wrong to me.
     
  5. Brownout

    Well-Known Member

    Jan 10, 2012
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    Yes, that schematic is very odd. Hurts my brain to think about it.
     
  6. Ron H

    AAC Fanatic!

    Apr 14, 2005
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    Yeah, something is definitely wrong there.
     
  7. t_n_k

    AAC Fanatic!

    Mar 6, 2009
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    If one removes the rather strange class B transistor pair (?) setup in the boxed section the circuit would reduce to a voltage doubler configuration - see attachment for possibly clearer layout.

    I think the U12 pin-outs are incorrect as shown in the OP's schematic. Perhaps this accounts for the simulation crash.

    Not sure what the part in the box is supposed to do - perhaps to provide some improved loading of the input side. It's probably a matter of some careful thinking to see if it works or not.
     
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  8. cougle

    Thread Starter New Member

    Mar 19, 2013
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    Yes TNK you are absolutely right, the rest is all a voltage doubler but couldn't figure out the purpose of push pull amplifier in this stage,what good purpose could it serve? maintaining constant current and voltage out of the doubler output or reducing ripple etc?

    Regarding the P-channel and n-channel devices at the input,to remove confusion, a more clearer schematic with pin names labelled is attached.

    The simulation goes correctly if I remove the transistor pair or connect the NPN in diode-connected configuration.
     
    Last edited: Mar 20, 2013
  9. t_n_k

    AAC Fanatic!

    Mar 6, 2009
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    I've been able to get the simulation running OK for the schematic you posted - albeit with different device type no.s and lower frequency.

    I can't really see the advantage (if any) in interposing the "buffer / follower" (my terminology) sub-circuit.

    In the simulations the added sub-circuit offers no benefit in terms of loading capability - in fact the performance appears marginally worse - so why include it?

    What are you actually trying to sort out anyway?
     
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  10. cougle

    Thread Starter New Member

    Mar 19, 2013
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    Well, that is my original question-
    This is a bias circuit of amplifier with a voltage regulator in cascade with this doubler.
    Could you please upload your simulations project?
     
  11. t_n_k

    AAC Fanatic!

    Mar 6, 2009
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    I'm using Simetrix for simulations. My models may not be of any use to you.

    You haven't really explained your reasons for doing the work - is this some equipment you are building or analyzing?
     
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  12. cougle

    Thread Starter New Member

    Mar 19, 2013
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    As I said this is the bias circuit of Amplifier. I am analyzing because there seems to be a problem with amplifier, So I wanted to check if the bias point or bias supply may have some problems.


    Anyway TNK thankyou so much for taking the time out to consider my problem.
     
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