PSpice vs built circuit advice please?

Discussion in 'The Projects Forum' started by asdfrewq, Dec 2, 2011.

  1. asdfrewq

    Thread Starter New Member

    Nov 25, 2011
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    Needing a little help. Yes, I am a student and this is a project. I am returning to school part-time after working for 20 years, so I am not looking for someone to do my work but I would like someone to tell me where I can look, or advise some “rules of thumb” I can use for the project below. This is Electrical Engineering which does not perfectly match my background but it is a topic I am interested in.

    Our project is to build a 3 stage amplifier, PSpice and actual circuit. I have a model in PSpice that meets all of the design criteria but when I actually build the circuit it is losing the AC components. DC is close all the way through the circuit. I have a schematic I can upload tonight but I really am looking for direction on why it does not match actual circuits and how I can improve the design, hoping it is around bias values. Had a couple of design that were a little too complex for me solve (All MOSFET w/mirror and Darlington pair designs) so I have switch back to the simplest design I can thank of MOSFET, BJT, BJT. I have quite a bit of info on the design so if you feel you can help and need more info I do not mind sharing.

    Criteria
    Gain =50, Rin^200k, RL=50, distortion <-30dB

    Design
    3 stage
    MOSFET and BJT

    Stage 1
    Biased MOSFET (no Rs)
    PSpice gain .95, Actual gain .45

    Stage 2
    Biased BJT 2N2222 Common Emitter (no Rs)
    PSpice gain 14 Actual 4

    Stage 3
    BJT 2N2222 Common Collector
    PSpice gain 51 Actual .9

    Possible problems I see:
    Is current messing me up? Starting with 5VDC and 10mVPP signal
    Everything look like it is the correct region, MOSFET=Saturation, BJT=Active, maybe I am wrong
    Add Rs to stabilize circuit, temperature seems to have some impact
    Are the PSpice components design correctly? Given to us by instructor but are they accurate enough?
    Will balancing the BJT bias help?
    MOSFET is 620k||500K in PSpice for the same DC values through the entire system I need 639k||300K. In PSpice the actual best seem to be a ratio of the PSpice numbers.

    Thanks,
    asdfrewq
     
  2. SgtWookie

    Expert

    Jul 17, 2007
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    It would help a great deal to see your schematic, as we can't really divine what may be in your netlist from what you've posted.

    Please post your schematic in .png image format. Size the schematic so it fits on your screen, then Ctrl+PrintScreen, paste it into MSPaint, crop to suit, and save as .png. Then come back on here, click the "Go Advanced" button, then "Manage Attachments" - it's sort of self-explanatory after that.

    If you are using relatively low values of resistance, that would explain having poor gain with real vs simulated parts.
     
  3. asdfrewq

    Thread Starter New Member

    Nov 25, 2011
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    Thanks for the quick reply. I am working through this try to understand the gap between PSpice and the actual circuit. Any advice is appreciated. "End of the day" I just need to have a working circuit but between now and then I would like to learn a little. I might want to use this some day without having to ask for someone to hold my hand.
     
  4. asdfrewq

    Thread Starter New Member

    Nov 25, 2011
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    One comment: The best DC values are when R7 = 640k
     
  5. thatoneguy

    AAC Fanatic!

    Feb 19, 2009
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    Common collector (final) stage has a voltage gain of 1 at most. It does have high current gain and low output impedance. Think of your last transistor as a current boosting unity gain stage.

    Try changing R2 or R10 (collector resistor on 2nd stage) to 10k and emitter resistor (R15?) to 150 and post results.
     
    Last edited: Dec 2, 2011
  6. asdfrewq

    Thread Starter New Member

    Nov 25, 2011
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    I had an incorrect statement about my gain thanks to thatoneguy for commenting on the CC for me to correct my info.

    V(A)/V(in) =2.18
    V(B)/V(in) =55 (between 100Hz and 30kHz)
    V(C)/V(in) =51 (between 100Hz and 30kHz)
     
  7. thatoneguy

    AAC Fanatic!

    Feb 19, 2009
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    Is that your measured gain, or simulated gain now?
     
  8. asdfrewq

    Thread Starter New Member

    Nov 25, 2011
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    I think that may be the wrong direction wiped out my overall gain. See attachment. What is your reasoning for suggesting the change is there a formula or process I should be following? Also the resistor on the collector side was R2 sorry for the messy schematic.
     
  9. asdfrewq

    Thread Starter New Member

    Nov 25, 2011
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    Simulated. I do not have a variable power supply at home. My simulated are good it is the actual values that underperform.
     
  10. thatoneguy

    AAC Fanatic!

    Feb 19, 2009
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    Gain is Rc/Re, roughly. The changed values put the current through that transistor much lower. Change them back, and try changing the 50 ohm emitter resistor to 25 ohm.

    Trying to get an idea of how messing up stuff makes other stuff mess up. Stability, sort of.

    This is learning, did I tell you I'm not much good at this stuff? :p
     
  11. asdfrewq

    Thread Starter New Member

    Nov 25, 2011
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    I change everything back and made R15 25 Ohms. It made Vout/Vin =61 in simulation.

    I spent all last weekend revising the circuit and simplifying trying to get a good system. That is why I went back to this design. The Darlington Pair seem to give me more variation that I was willing to wade through, same goes for MOSFETs. I learned a lot, namely, "this stuff is hard" and "these kids are a lot smarter than me". Great for the pride.
     
    Last edited: Dec 2, 2011
  12. thatoneguy

    AAC Fanatic!

    Feb 19, 2009
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    Post back when you are near it. Real life it may be clipping or biased too high/low, though it looks correct.

    Don't get many questions with amps using a MOSFET input stage. Most of the voltage gain should be in 2nd stage. Input stage is for high impedance and correct frequency response, Output stage is for low impedance and high current drive.
     
  13. asdfrewq

    Thread Starter New Member

    Nov 25, 2011
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    In this comment do you mean there may be loss in gain due to the ratio or size of these two resistors? I have been playing with it in PSpice and the low side seems to clip fairly quickly and increase my distortion. I am understanding the second stage to be the work horse of the circuit, I was thinking it was the biasing that contributed to the error but it sounds like Rc&Re are bigger contributors. Is that an accurate statement?
     
  14. thatoneguy

    AAC Fanatic!

    Feb 19, 2009
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    Yes, Rc and Re are the major parts that determine gain, you also want to keep the quiescent current Ice in the operating range (emitter and collector resistors), just as you keep the bias resistors in the same operating area, so these values change somewhat in conjunction with the bias resistors to stay in the correct operating range.

    e-Book Section
     
  15. Adjuster

    Well-Known Member

    Dec 26, 2010
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    This is not an unreasonably hard problem, but it may not be easy to get good agreement between the model and the practical because of some of the circuit values chosen. In the circuit posted, Q1 base resistors R2 and R1 are too large for good bias stability with typical hFE or β of ≈ 100. That β value I will assume for the 2N2222, but it is it is actually subject to large spreads, hence the need for caution in designing the circuit.

    It would be more usual to have the base chain passing about ten times more current than the expected base current, (or perhaps ten times less than the collector current, depending on the expected hFE). This is not a hard-and-fast rule but a guide: sometimes base resistors this low are not desirable and a compromise is required.

    For stability, it is also desirable to have a fairly big voltage across the emitter resistor: not so big as to reduce the available signal swing too far, but even in a low voltage circuit like this, half a volt might be reasonable. This may require more resistance than needed to set the AC gain, but a capacitor may be added if necessary to bypass part of the resistance at signal frequencies.

    Another problem is the loading of the input impedance of one stage upon the output of the stage feeding it. With bipolar transistors, this is related to the rather unpredictable current gain, which may play a part in your disappointing results.

    In your case the collector current of Q1 might reasonably be about 1.33mA, to set the collector a couple of volts down from the supply with a 1.5kΩ load. The emitter resistance required to drop 0.5V would then be 375Ω (360Ω or 390Ω preferred).

    The base chain would requite attention next. Let us estimate that the base current is 1.333mA/100 = 13.33μA. The upper base resistor R2 might pass ten times that much, the lower resistor R1 nine times. If we assume Q1 VBE = 0.6V, the base voltage is 1.1V, so the lower resistor R1 is 1.1V/(9*13.33μA) = 9.17kΩ (9.1kΩ). The upper resistor R2 is (5V-1.1V)/(10*13.33μA) = 29.25kΩ (30kΩ). Note that if only limited resistor values were available in the school lab. it should be acceptable to go up one step on both resistors. making R1 10kΩ, R2 33kΩ.

    To assess the voltage gain of Q1, note that its collector load is reduced by the input impedance of Q3. This is of order (β+1)*(total emitter loading) ≈101*(re3+ 100//50) ≈ 3.5kΩ. Under these circumstances it is probably reasonable to ignore the transistor's own collector slope resistances, which should be at least an order of magnitude bigger. The effective load on Q1 is then Rctotal = (1.5kΩ//3.5kΩ) = 1.05kΩ.

    The loaded gain is roughly Rctotal / (RE1+re1)= 1.05kΩ/(RE1 + 26mV/Ie1) If the external emitter resistor is bypassed by a capacitor to ground, effectively the AC RE=0 and the gain is ≈ 1.05kΩ/19.5Ω = 54 times. If RE is not bypassed the gain would drop to 1.05/(19.5+360) = 2.77times. Using two resistors and a bypass capacitor, intermediate gains are possible.

    Now for this stage input impedance. The heavy bias chain will drop it a bit (10kΩ//33kΩ = 7.67kΩ). Q1 base input impedance about (β+1)(RE + re). With RE=0, ie completely AC bypassed, this would be roughly 101*(26Ω/1.33) = 1.97kΩ, but with no bypass capacitor this would rise to 101*(19.5Ω+360Ω) = 38.33kΩ. The total input impedance thus comes to anything between (1.97kΩ//7.67kΩ) =1.57kΩ and (38.33kΩ//7.67kΩ) = 6.39kΩ

    This is a heavy load on M1 in comparison with the 15kΩ drain resistor R8. It may therefore be sensible to reduce this.

    After all this talk, let's try a simulation. I don't have a model of your FET in my freebie LTSpice simulator, and it seems that the nearest available device gives a lot more gain than you had. It was necessary to add a source resistor to get the gain low enough, even with Q1 gain turned well down with 100Ω un-bypassed RE. You can of course reduce or omit that extra resistor (R5) as necessary, and / or reduce R16 if your FET has much lower gm.

    Note also that in this version the bias for the output follower comes directly from Q1 collector, to save a few parts and some loading at that point. Note that 20kΩ bias resistors are a bit too high for a stage with only 100Ω emitter load. I have also put some feedback around the FET bias, as these things are a bit variable.
     
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  16. asdfrewq

    Thread Starter New Member

    Nov 25, 2011
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    Wow, thanks a lot to the Adjuster and Thatoneguy. The last post has a lot of info to digest, and thanks for the reasoning behind the changes. I am wanting to understand how to build good circuits based on the model and this type of notes will help me.

    Now I am going to sit here and play with circuit and see if I can get it to work. I am going to the lab on Sunday after lunch (Texas time). I will post how it is going and any other questions I have.
     
    Last edited: Dec 3, 2011
  17. asdfrewq

    Thread Starter New Member

    Nov 25, 2011
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    Adjuster, I just notice that you had an attachment with the schematic, it helps to play with a circuit that works but it is a slippery slope people can take the work as is. I have entered your schematic in PSpice and I was only getting a gain of around 15 using my MOSFET and some components I had. I think I will get my circuit to work correctly once I get in the lab.

    Your notes are great, my instructor is pretty good and he said all the math stuff it is just me not applying it correctly. The "rule of thumb" comments are helpful for getting an understanding of what is happening.

    Question on your circuit that I am not sure about.

    What is the impact of different size capacitors? I swap them around but I do not see a real change.

    What is the function of R3,R4,R7, C4? Is this a feedback for the MOSFET rather than biasing it? My understand on feedback is it reduces gain but stabilizes the circuit
    fo use in actual applications.
     
  18. asdfrewq

    Thread Starter New Member

    Nov 25, 2011
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    Your original message answered one of my questions around the feedback on the MOSFET.

    Another question: Was the only reason for not biasing the circuit to save components? My understand was this help with the sensitivity of the circuits.
     
  19. Adjuster

    Well-Known Member

    Dec 26, 2010
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    The size of the capacitors mainly affects the low frequency response, that is, the frequencies below which the capacitor reactances become comparable with the circuit impedances, causing losses. Thus for a given frequency, more capacitance is needed in lower impedance circuits.

    If you look at the frequency response graphs, you will see that the output capacitor to the load gives the most low frequency loss, although it is the biggest - perhaps it could be bigger. If 100μF is taken to be adequate for the output into 50Ω however, the smaller values of the other capacitors are probably adequate, as they are working in kΩ impedances. You might like to check what low frequency cut-off is actually required.

    The input capacitor is small partly because it is in a high impedance circuit. Not only are lower values tolerable here, but they may be desirable because they make it more convenient to avoid electrolytic capacitors, whose higher leakage currents might upset the DC conditions.

    In my version of this circuit, I also had to play around with the coupling capacitor values of the first stage as well as the bias decoupling cap C4 to get a reasonable frequency response when I added that input bias circuit. This has a potential hazard of turning into a phase-shift oscillator, or at least giving an LF gain peak (avoiding that is what the lead/lag bit with C4 & R4 is about).

    With a different FET from the ones I could simulate, you may find it safer to go back to fixed bias at the input. If you do that though, be sure to check the drain voltage is somewhere near half supply - if not alter the gate resistors as required to fix this. The FET gate threshold voltage could well be a bit off what you expect, so that the FET may be turned on too much or not enough, which can easily wreck the gain. Feedback bias eases this problem.

    Partly it was to save components, as well as a bit of my time.:p Seriously though, to get the bias nice and stable for that transistor, the bias resistors would have had to drop in value quite a lot. If the final transistor emitter was at 2.5V, the emitter current is 25mA, so at β = 100 the base current is 250μA. If we try to get bias resistors passing 10 times that (2.5mA) we would end up having them about 1kΩ each, which would load the previous stage a lot.

    It will be simpler just to connect the base straight to the previous collector, provided that its DC voltage is suitable, which it should be. You will find that the DC base current from the last stage pulls that collector voltage down a bit, but it should be tolerable.
     
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  20. asdfrewq

    Thread Starter New Member

    Nov 25, 2011
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    thanks for all the info!!!!

    My instructor gave us an alternate component to use in psice I think some of the values may need to new adjusted, he has asked a couple of times if we verified the I am going to do that now.
     
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