Pspice from two good inputs xor gate creates a bad output in full adder

Discussion in 'Digital Circuit Design' started by JoyAm, Jul 20, 2016.

  1. JoyAm

    Thread Starter Member

    Aug 21, 2014
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    Hello everyone once more i have a spice problem the image is self explanatory i have no idea why this happens Screenshot_4.png
     
  2. WBahn

    Moderator

    Mar 31, 2012
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    What is "sum" connected to at a higher level? Do you have multiple devices driving that node?
     
  3. JoyAm

    Thread Starter Member

    Aug 21, 2014
    112
    4
    Hello and thanks for the reply the output of sum goes to a 16 bit bus i will attach a picture of the ascended hierarchy Screenshot_8.png
     
  4. WBahn

    Moderator

    Mar 31, 2012
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    I can't correlate this schematic to the sim signals next to it or to the prior schematic.
     
  5. JoyAm

    Thread Starter Member

    Aug 21, 2014
    112
    4
    The prior scematic is one of the full adders the sim signals are just some random cables from the inputs . The problem is that signals with valid values get into the adders and get out like X value signals
     
  6. WBahn

    Moderator

    Mar 31, 2012
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    But I can't tell WHICH adder the first sim results are from. I'm looking for a reference designator in the second schematic that ends in "gez" and I don't see one.

    Have you simulated the full adder separately and shown that it behaves as expected for all possible inputs? Since it only has three inputs, that shouldn't take long to set up.
     
  7. JoyAm

    Thread Starter Member

    Aug 21, 2014
    112
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    It is from the first FA, there are uper layers as well that i can put here if it helps the "gez" is the ending of level1.stagez i think you will understand once i provide the other screenshots . As for the adder i even used the build in component for 2 bit addition from the digprim library and i still got x sum Screenshot_9.png Screenshot_10.png
     
  8. JoyAm

    Thread Starter Member

    Aug 21, 2014
    112
    4
    I have been looking at it the whole day and i was making experiments changing the names of the cables, this lead me to have less cables with x name but they still exist. i will post the pictures bellow . Screenshot_11.png Screenshot_2.png Screenshot_1.png Screenshot_3.png Screenshot_4.png Screenshot_5.png Screenshot_6.png
     
  9. WBahn

    Moderator

    Mar 31, 2012
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    Have you simulated JUST this part of the circuit, completely disconnected from all higher level circuitry?
     
  10. JoyAm

    Thread Starter Member

    Aug 21, 2014
    112
    4
    Hello WBanh i spent many hours working on it testing different stuff etc and i managed to make it work. The problem was the names of the cables and buses i still have not understood how exactly it works but still thats the solution to the problem.
    Thanks a lot for your help all along :)
     
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