Project Counter Gray

Discussion in 'General Electronics Chat' started by elena_p, May 22, 2015.

  1. elena_p

    Thread Starter New Member

    May 22, 2015
    4
    0
    Hi , I'm trying to make a digital circuit that implements a 5-bit Gray code counter. I've tried simulating the circuit on ISP lever Classic Project and doesn't work.I have to use GALp16v8 :(
    I have the following errors:

    Input file: 'gray.tt2'
    Device 'p16v8'
    Note 4161: Using device architecture type P16V8R.
    Warning 4034:Unable to preserve preassignments - performing second pass without preassignments.
    Note 4059: Signal Q0 cannot be assigned (to pin 16) because
    there are too many terms for output Q0 pin 16.

    Note 4046: Signal Q1 (which has no OE) has been
    assigned to pin 15 (which has pin OE).
    Note 4046: Signal Q2 (which has no OE) has been
    assigned to pin 14 (which has pin OE).
    Note 4046: Signal Q3 (which has no OE) has been
    assigned to pin 13 (which has pin OE).
    Note 4046: Signal Q4 (which has no OE) has been
    assigned to pin 12 (which has pin OE).
    Design does NOT fit

    FIT complete. Time: 1 second.

    Done: failed with exit code: 0001.
     
  2. elena_p

    Thread Starter New Member

    May 22, 2015
    4
    0
    CODE:

    MODULE Counter_Gray

    TITLE 'Counter_Gray_5_bit'

    declarations

    clock,reset pin 1,2;
    Y pin 3;
    Q0,Q1,Q2,Q3,Q4 pin 12,13,14,15,16 istype 'reg';


    "state definition

    QSTATE=[Q4,Q3,Q2,Q1,Q0];
    S0=[0,0,0,0,0];
    S1=[0,0,0,0,1];
    S2=[0,0,0,1,1];
    S3=[0,0,0,1,0];
    S4=[0,0,1,1,0];
    S5=[0,0,1,1,1];
    S6=[0,0,1,0,1];
    S7=[0,0,1,0,0];
    S8=[0,1,1,0,0];
    S9=[0,1,1,0,1];
    S10=[0,1,1,1,1];
    S11=[0,1,1,1,0];
    S12=[0,1,0,1,0];
    S13=[0,1,0,1,1];
    S14=[0,1,0,0,1];
    S15=[0,1,0,0,0];
    S16=[1,1,0,0,0];
    S17=[1,1,0,0,1];
    S18=[1,1,0,1,1];
    S19=[1,1,0,1,0];
    S20=[1,1,1,1,0];
    S21=[1,1,1,1,1];
    S22=[1,1,1,0,1];
    S23=[1,1,1,0,0];
    S24=[1,0,1,0,0];
    S25=[1,0,1,0,1];
    S26=[1,0,1,1,1];
    S27=[1,0,1,1,0];
    S28=[1,0,0,1,0];
    S29=[1,0,0,1,1];
    S30=[1,0,0,0,1];
    S31=[1,0,0,0,0];

    equations

    QSTATE.clk=clock;

    when ( Y==0 ) then {
    when (reset == 0) then QSTATE := S0;
    else when (QSTATE == S0) THEN QSTATE := S1;
    else when (QSTATE == S1) THEN QSTATE := S2;
    else when (QSTATE == S2) THEN QSTATE := S3;
    else when (QSTATE == S3) THEN QSTATE := S4;
    else when (QSTATE == S4) THEN QSTATE := S5;
    else when (QSTATE == S5) THEN QSTATE := S6;
    else when (QSTATE == S6) THEN QSTATE := S7;
    else when (QSTATE == S7) THEN QSTATE := S8;
    else when (QSTATE == S8) THEN QSTATE := S9;
    else when (QSTATE == S9) THEN QSTATE := S10;
    else when (QSTATE == S10) THEN QSTATE := S11;
    else when (QSTATE == S11) THEN QSTATE := S12;
    else when (QSTATE == S12) THEN QSTATE := S13;
    else when (QSTATE == S13) THEN QSTATE := S14;
    else when (QSTATE == S14) THEN QSTATE := S15;
    else when (QSTATE == S15) THEN QSTATE := S16;
    else when (QSTATE == S16) THEN QSTATE := S17;
    else when (QSTATE == S17) THEN QSTATE := S18;
    else when (QSTATE == S18) THEN QSTATE := S19;
    else when (QSTATE == S19) THEN QSTATE := S20;
    else when (QSTATE == S20) THEN QSTATE := S21;
    else when (QSTATE == S21) THEN QSTATE := S22;
    else when (QSTATE == S22) THEN QSTATE := S23;
    else when (QSTATE == S23) THEN QSTATE := S24;
    else when (QSTATE == S24) THEN QSTATE := S25;
    else when (QSTATE == S25) THEN QSTATE := S26;
    else when (QSTATE == S26) THEN QSTATE := S27;
    else when (QSTATE == S27) THEN QSTATE := S28;
    else when (QSTATE == S28) THEN QSTATE := S29;
    else when (QSTATE == S29) THEN QSTATE := S30;
    else when (QSTATE == S30) THEN QSTATE := S31;
    else when (QSTATE == S31) THEN QSTATE := S0;
    }
    else
    QSTATE := QSTATE;

    Test_Vectors ([reset,clock,Y]->[Q4,Q3,Q2,Q1,Q0])
    [0, .c., .x.]->[0,0,0,0,0];
    [1, .c., 1 ]->[0,0,0,0,1];
    [1, .c., 1 ]->[0,0,0,1,1];
    [1, .c., 1 ]->[0,0,0,1,0];
    [1, .c., 1 ]->[0,0,1,1,0];
    [1, .c., 1 ]->[0,0,1,1,1];
    [1, .c., 1 ]->[0,0,1,0,1];
    [1, .c., 1 ]->[0,0,1,0,0];
    [1, .c., 1 ]->[0,1,1,0,0];
    [1, .c., 1 ]->[0,1,1,0,1];
    [1, .c., 1 ]->[0,1,1,1,1];
    [1, .c., 1 ]->[0,1,1,1,0];
    [1, .c., 1 ]->[0,1,0,1,0];
    [1, .c., 1 ]->[0,1,0,1,1];
    [1, .c., 1 ]->[0,1,0,0,1];
    [1, .c., 1 ]->[0,1,0,0,0];
    [1, .c., 1 ]->[1,1,0,0,0];
    [1, .c., 1 ]->[1,1,0,0,1];
    [1, .c., 1 ]->[1,1,0,1,1];
    [1, .c., 1 ]->[1,1,0,1,0];
    [1, .c., 1 ]->[1,1,1,1,0];
    [1, .c., 1 ]->[1,1,1,1,1];
    [1, .c., 1 ]->[1,1,1,0,1];
    [1, .c., 1 ]->[1,1,1,0,0];
    [1, .c., 1 ]->[1,0,1,0,0];
    [1, .c., 1 ]->[1,0,1,0,1];
    [1, .c., 1 ]->[1,0,1,1,1];
    [1, .c., 1 ]->[1,0,1,1,0];
    [1, .c., 1 ]->[1,0,0,1,0];
    [1, .c., 1 ]->[1,0,0,1,1];
    [1, .c., 1 ]->[1,0,0,0,1];
    [1, .c., 1 ]->[1,0,0,0,0];

    END
     
  3. JWHassler

    Member

    Sep 25, 2013
    201
    33
    The Note 4059 is important: but no onme can say what the reasons is without a look at the logic

    The next four 4046's can probably be disregarded for now. If the compiler can make the design fit, let it do so.
    Again, a look at the logic would help.
    Also- why do you need an Output Enable on your counter?
     
  4. elena_p

    Thread Starter New Member

    May 22, 2015
    4
    0
    This is the problem:I don't need it.And I don't use it .
    All i have to do is: make a digital circuit that implements a 5-bit Gray code counter with priority reset.
     
  5. AnalogKid

    Distinguished Member

    Aug 1, 2013
    4,538
    1,251
  6. elena_p

    Thread Starter New Member

    May 22, 2015
    4
    0
    Thanks for your reply . But this will not help me.
     
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