programmable parallel to serial converter

Discussion in 'General Electronics Chat' started by ideas, Mar 16, 2012.

  1. ideas

    Thread Starter New Member

    Mar 16, 2012
    can any1 help me in writing a vhdl r verilog code for 6 to 16 bit programmable parallel to serial converter....
    I have written the code but iam getting some errors plz help me....
    library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity P2S is port ( Serial_out : out std_logic; clk : in std_logic; Parallel_data : in std_logic_vector(15 downto 0); DataReady : in std_logic); end P2S; architecture Behavioral of P2S is Signal Shreg : std_logic_vector( 15 downto 0); begin process( clk) variable x : integer := 6; begin if DataReady = '1' then if (clk'event and clk = '1') then x := x+1; for i in 0 to x loop if(parallel_data = i) then Shreg <= parallel_data; else Shreg <= Shreg(0) & Shreg(x downto 1); end if; end loop; end if; else Serial_out <= Shreg(0); End if; End process; End Behavioral;
    ERROR:Xst:1549 - "D:/Anjali/ANJALI/p2s/p2s.vhd" line 52: Range bound must be a constant.
    help me how this can be rectified