yes that's very Informative . But I Think I am too long from this project. I am interested to DO that project . can you give me some idea how can I do that project step by step with very few duration. I don't believe that I can Do such big projects
Processor Registers
- Thread starter abhimanyu143
- Start date
All the more reason to look at the Nand2Tetris project. If you work through that project diligently, you will have a very good understanding of the basic concepts behind a modern computing system. Not everything and what you do know will be somewhat limited and shallow, but you will be amazed how much more all of this will make sense to you.
When I did that project from the time that I started downloading the software from their site to the time I had the first five projects completed took about three hours and these are the projects that get at the heart of what you are struggling with here. Don't expect to finish them that fast because I had the advantage of having a solid understanding of these concepts before I started, but the early projects are quite tractable. The later projects become progressively more involved, but you can save those for later.
You can also do the projects in any order, but I recommend doing them in the order presented.
Decoder used in processor
Look this link http://en.wikipedia.org/wiki/Decoder
there are two type of decoder
In post 18 , the Instruction is 8 bit . and 256 instruction , To decode 256 instruction I think we need 8x256 Decoder
but there is not sufficient Information In this link about decoder
some one can tell me How does decoder decode instruction?
Look this link http://en.wikipedia.org/wiki/Decoder
there are two type of decoder
- Instruction Decoder
- Address decoder
In post 18 , the Instruction is 8 bit . and 256 instruction , To decode 256 instruction I think we need 8x256 Decoder
but there is not sufficient Information In this link about decoder
some one can tell me How does decoder decode instruction?
Vead, just like I said in the other thread. The decoder is similar to a table, where for each instruction the apropriate outputs connected to control wires that go to each part of the processor are turend on or off.
So for example if the instruction is ADD A the wires are set such that the output of register A is connected to one input of the ALU, accumulator is is connected to the other input and the result will be stored back to the accumulator.
Without talking about some actual design and having it in front of me it is quite hard to explain thing in this abstract manner.
Google how for examle a 3-to-8 decoder works. Now imagine that you have a similar decode wired such that for each instruction the correct control wires are activated. That is the decoder.
So for example if the instruction is ADD A the wires are set such that the output of register A is connected to one input of the ALU, accumulator is is connected to the other input and the result will be stored back to the accumulator.
Without talking about some actual design and having it in front of me it is quite hard to explain thing in this abstract manner.
Google how for examle a 3-to-8 decoder works. Now imagine that you have a similar decode wired such that for each instruction the correct control wires are activated. That is the decoder.
Chapter 5 of the Nand2Tetris project.
this link show truth table of decoder http://coep.vlab.co.in/?sub=28&brch=81&sim=609&cnt=1
suppose we have three control wires.
one wire for accumulator
one wire for registers
one wire for memory
Example
3 to 8 decoder
000 no wires are activate
001 memory wire is activate
010 register wire is activate
011 register and memory wires are activate
100 accumulator wire is activate
101 accumulator and memory wires are activated
110 accumulator and register wires are activate
111 all wires are activated
Did you mean like this type of example
output of each instruction is connected with Accumulator
100 accumulator wire is activate
100 LD A
100 ADD A
100 SUB A
100 MUL A
100 AND A
100 OR A
010 register wire is activate
010 LD R
010 ADD R
010 SUB R
010 AND R
010 OR R
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So you are actually vead. kubeek is much faster than me to recognise you...
From your way of writing: "I looked that post" you never use preposition like "at". And
you never terminate a sentence with full-stop. You just start with another line.....etc
What's wrong with the old name "vead". Are you scared that no one would help you if you continue using the old name?
Dont worry about how we can sometimes get frustrated helping members. But after a while everything will be back to normal and we'll be helping again. This happens all the time.
Allen
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Am I need to proof That I am abhimanyu.? the post is on same topic but I already said that there are many student that are studying course on embedded system in indiaSo you are actually vead. kubeek is much faster than me to recognise you...
From your way of writing: "I looked that post" you never use preposition like "at". And
you never terminate a sentence with full-stop. You just start with another line.....etc
What's wrong with the old name "vead". Are you scared that no one would help you if you continue using the old name?
Dont worry about how we can sometimes get frustrated helping members. But after a while everything will be back to normal and we'll be helping again. This happens all the time.
Allen
so topic may be same and yes I don't understand English very well I except that there are many similarity between me and that guy because we both belong to same place India. even doing same degree course
there are many student that face this problem
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I have only 4 topics to read then I will start PiC controller
timer
interrupt
uart
A to D converter
Interrupt an interrupt is a signal to the processor emitted by hardware
Hardware interrupts are used by devices to communicate that they require attention from the operating system.
link http://en.wikipedia.org/wiki/Interrupt
How does interrupt generate in microcontroller circuit ?
timer
interrupt
uart
A to D converter
Interrupt an interrupt is a signal to the processor emitted by hardware
Hardware interrupts are used by devices to communicate that they require attention from the operating system.
link http://en.wikipedia.org/wiki/Interrupt
How does interrupt generate in microcontroller circuit ?
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I apologize if you are not vead. Please don't get upset about this...
Anyway, AAC is a very nice forum where members here are very helpful and friendly. I hope you'll have a present stay and learn as much as you wish...
Allen
Interrupt http://www.embedidea.com/8051-interrupt-tutorial/
Interrupt registers
Interrupt registers
- IE Register(Interrupt Enable)
- IP Register(Interrupt Priorities)
Interrupt sets a certain bit in Status register. At the beginning of each instruction cycle the controller check this bit, and if it is set then instead of fetching the next intruction it stores Program counter to some known location (so that it can later go back to where it left) and starts exectuing the intructions for the interrupt. After the interrupt routine finishes, the previously stored program counter is restored and the normal program continues.
I am talking about only Instruction decoder
I think this two link may be useful
3. Decode Instruction Phase http://www.c-jump.com/CIS77/CPU/InstrCycle/lecture.html
this link show truth table of decoder http://coep.vlab.co.in/?sub=28&brch=81&sim=609&cnt=1
I am trying to do something from 1 st link
suppose we have three control wires.
one wire for accumulator
one wire for registers
one wire for memory
Example
3 to 8 decoder
000 no wires are activate
001 memory wire is activate
010 register wire is activate
011 register and memory wires are activate
100 accumulator wire is activate
101 accumulator and memory wires are activated
110 accumulator and register wires are activate
111 all wires are activated
Did you mean like this type of example
output of each instruction is connected with Accumulator
100 accumulator wire is activate
100 LD A
100 ADD A
100 SUB A
100 MUL A
100 AND A
100 OR A
010 register wire is activate
010 LD R
010 ADD R
010 SUB R
010 AND R
010 OR R
I am trying to understand Instruction decoder . I understood truth table of decoder But I am not understanding how does instruction decoder decode instruction and how does particular source or destination turn on/off
Look at this diagram http://www.nt-nv.fh-koeln.de/Labor/VhdlEnglish/Kap8/k832.html Near the bottom you can see which control wires are activated for each instruction opcode.
And here is VHDL code for it
And here is VHDL code for it
Code:
-- VHDL-Modell der TOY-Simulation -----------------------------------
---------------------------------------------------------------------
PACKAGE a2 IS
TYPE ltg IS ARRAY(1 TO 2) OF integer;
END a2;
-- VHDL-Beschreibung der ALUaccu
ENTITY ALUaccu IS
GENERIC(T : Time := 4 ns);
PORT(ramdat, alucon : IN ltg;
aluout : OUT ltg;
nullflag : OUT integer);
END ALUaccu;
ARCHITECTURE behaviour OF ALUaccu IS
BEGIN
PROCESS
TYPE word IS ARRAY(1 TO 16) OF integer;
VARIABLE oldclk, adress, opcode, adi, opi, opo, ado : integer :=0;
VARIABLE oldalucon, vopout, vadout, temp, i, j : integer :=0;
VARIABLE acbit, rambit, outbit : word;
BEGIN
IF alucon(1) /= oldalucon THEN
temp:=ado;
FOR j IN 1 TO 12 LOOP
IF temp < 1 THEN
acbit(j):=0;
ELSE
acbit(j):=temp MOD 2; temp:=(temp-(temp MOD 2))/2;
END IF;
END LOOP;
temp:=opo;
FOR j IN 13 TO 16 LOOP
IF temp < 1 THEN
acbit(j):=0;
ELSE
acbit(j):=temp MOD 2; temp:=(temp-(temp MOD 2))/2;
END IF;
END LOOP;
temp:=ramdat(2);
FOR j IN 1 TO 12 LOOP
IF temp < 1 THEN
rambit(j):=0;
ELSE
rambit(j):=temp MOD 2; temp:=(temp-(temp MOD 2))/2;
END IF;
END LOOP;
temp:=ramdat(1)
FOR j IN 13 TO 16 LOOP
IF temp < 1 THEN
rambit(j):=0;
ELSE
rambit(j):=temp MOD 2; temp:=(temp-(temp MOD 2))/2;
END IF;
END LOOP;
IF alucon(1)=12 THEN vopout:=opo; vadout:=ado;
ELSIF alucon(1)=1 THEN
vopout:=ramdat(1); vadout:=ramdat(2);
ELSIF alucon(1)=3 THEN
vopout:=opo+ramdat(1); vadout:=ado+ramdat(2);
ELSIF alucon(1)=4 THEN
vopout:=opo-ramdat(1); vadout:=ado-ramdat(2);
ELSIF alucon(1)=5 THEN
FOR i IN 1 TO 16 LOOP
IF (acbit(i)=1) OR rambit(i)=1) THEN
outbit(i):=1;
ELSE
outbit(i):=0;
END IF;
END LOOP;
ELSIF alucon(1)=6
FOR i IN 1 TO 16 LOOP
IF (acbit(i)=1) AND rambit(i)=1) THEN
outbit(i):=1;
ELSE
outbit(i):=0;
END IF;
END LOOP;
ELSIF alucon(1)=7
FOR i IN 1 TO 16 LOOP
IF (acbit(i)=1) /= rambit(i)=1) THEN
outbit(i):=1;
ELSE
outbit(i):=0;
END IF;
END LOOP;
ELSIF alucon(1)=8
FOR i IN 1 TO 16 LOOP
IF (acbit(i)=1) = rambit(i)=1) THEN
outbit(i):=1;
ELSE
outbit(i):=0;
END IF;
END LOOP;
ELSIF alucon(1)=9 THEN vopout:=opo; vadout:=ado+1;
ELSIF alucon(1)=10 THEN vopout:=opo; vadout:=ado-1;
ELSIF alucon(1)=11 THEN vopout:=0; vadout:=0;
END IF;
END IF;
IF alucon(1)>4 AND alucon(1)<9 THEN
vadout:=0;
FOR i IN 1 TO 12 LOOP
vadout:=vadout + (outbit(i)*(2**(i-1)));
END LOOP; vopout := 0;
FOR i IN 13 TO 16 LOOP
vopout:=vopout + (outbit(i)*(2**(i-13)));
END LOOP;
END IF;
oldalucon:=alucon(1);
IF alucon(2) =1 AND oldclk=0 THEN
opo:=vopout; ado:= vadout;
END IF;
IF opo=0 AND ado=0 THEN
nullflag<=1 AFTER T;
ELSE
nullflag<=0 AFTER T;
END IF;
oldclk:=alucon(2); aluout(1)<=vopout AFTER T; aluout(2) <= vadout AFTER T;
END PROCESS;
END behaviour;
-- VHDL-Beschreibung des Programmzaehlers (PC)
ENTITY PC IS
GENERIC(T : Time := 4ns);
PORT(iri, nflag : IN integer;
clock : IN ltg;
outa : OUT integer);
END PC;
ARCHITECTURE behaviour OF PC IS
BEGIN
PROCESS
VARIABLE addr, oldclock, oldsddr, oldinc : integer:=0;
BEGIN
IF clock(1)=1 AND oldclock=0 AND nflag=1 THEN
addr:=iri;
END IF;
IF clock(2)=1 AND oldinc=0 THEN
addr:=(oldaddr+1);
END IF;
outa<=addr AFTER T;
oldclock:=clock(1);
oldaddr:=addr;
oldinc:=clock(2);
END PROCESS;
END behaviour;
-- VHDL-Beschreibung des Multiplexers (Mux)
ENTITY Mux IS
GENERIC(T : Time := 2ns);
PORT(ir, pc : IN integer;
addrir : IN ltg;
adout : OUT integer);
END Mux;
ARCHITECTURE behaviour OF Mux IS
BEGIN
PROCESS
VARIABLE oldaddrir, vout, oldaddrpc : integer:=0;
BEGIN
IF addrir(1)=1 AND oldaddrir=0 THEN
vout:=ir;
END IF;
IF addrir(2)=1 AND oldaddrpc=0 THEN
vout:=pc;
END IF;
adout<=vout AFTER T;
oldaddrir:=addrir(1);
oldaddrpc:=addrir(2);
END PROCESS;
END behaviour;
-- VHDL-Beschreibung des Befehlsregisters (IR)
ENTITY IR IS
GENERIC(T : Time := 4 ns);
PORT(ramin : IN ltg;
clockir : IN integer;
opcon, adpc: OUT integer);
END IR;
ARCHITECTURE behaviour OF IR IS
BEGIN
PROCESS
VARIABLE oldclockir, vadpc, vopcon : integer := 0;
BEGIN
IF clockir=1 AND oldclockir=0 THEN
vadpc:=ramin(2);
vopcon:=ramin(1);
END IF
adpc <= vadpc AFTER T;
opcon <= vopcon AFTER T;
oldclockir:=clockir;
END PROCESS;
END behaviour;
-- VHDL-Beschreibung des Steuerwerks (Control)
ENTITY Control IS
GENERIC(T : Time := 2ns);
PORT(opco, takt : IN integer;
clir, wriram : OUT integer;
alcon, adir, clpc : OUT ltg);
END Control;
ARCHITECTURE behaviour OF Control IS
BEGIN
PROCESS
VARIABLE oldtakt, vclac, vclir, valcon, vadir : integer;
VARIABLE vadpc, count, vclpc : integer;
VARIABLE vwriram, vincpc, anfang : integer;
BEGIN
IF takt=1 AND oldtakt=0 AND count=0
IF opco=12 THEN
vadir:=1; vadpc:=0; valcon:=opco; vwriram:=1;
vclac:=0; vclir:=0; vclpc:=0; vincpc:=0;
ELSIF opco=1 THEN
vadir:=1; vadpc:=0; valcon:=opco; vwriram:=0;
vclac:=1; vclir:=0; vclpc:=0; vincpc:=0;
ELSIF opco=2 THEN
vadir:=0; vadpc:=1; valcon:=opco; vwriram:=0;
vclac:=0; vclir:=0; vclpc:=1; vincpc:=0;
ELSIF opco>2 AND opco<8 then
vadir:=1; vadpc:=0; valcon:=opco; vwriram:=0;
vclac:=1; vclir:=0; vclpc:=0; vincpc:=0;
ELSIF opco=8 THEN
vadir:=0; vadpc:=1; valcon:=opco; vwriram:=0;
vclac:=1; vclir:=0; vclpc:=0; vincpc:=0;
ELSIF opco=9 THEN
vadir:=0; vadpc:=0; valcon:=opco; vwriram:=0;
vclac:=1; vclir:=0; vclpc:=0; vincpc:=0;
ELSIF opco=10 THEN
vadir:=0; vadpc:=1; valcon:=opco; vwriram:=0;
vclac:=1; vclir:=0; vclpc:=0; vincpc:=0;
ELSIF opco=11 THEN
vadir:=0; vadpc:=1; valcon:=opco; vwriram:=0;
vclac:=1; vclir:=0; vclpc:=0; vincpc:=0;
ELSIF opco=0 OR opco>12 THEN
IF anfang=0 THEN
vadpc:=0; vclir:=1;
vincpc:=1; anfang:=1;
ELSE
vadir:=0; vadpc:=1; valcon:=opco; vwriram:=0;
vclac:=0; vclir:=1; vclpc:=0; vincpc:=1;
END IF;
END IF;
END IF;
IF takt=1 AND oldtakt=0 AND count=1 THEN
vadir:=0; vadpc:=1; vclir:=1; vincpc:=1;
valcon:=0; vwriram:=0; vclac:=0; vclpc:=0;
END IF;
IF takt=1 AND oldtakt=0 AND opco<13 AND opco>0 AND count=0 THEN
count:=1;
ELSIF takt=1 AND oldtakt=0 THEN
count:=0;
END IF;
IF takt=0 AND oldtakt=1 THEN
vadir:=0; vadpc:=0; valcon:=0; vwriram:=0;
vclac:=0; vclir:=0; vclpc:=0; vincpc:=0;
END IF;
adir(1) <= vadir AFTER T;
adir(2) <= vadpc AFTER T;
alcon(1)<=valcon AFTER T + 12 ns;
wriram<=vwriram AFTER T+16 ns;
alucon(2) <=vclac AFTER T+12 ns;
clir <= vclir AFTER T + 15 ns;
clpc(2)<=vinpc AFTER T + 16 ns;
clpc(1)<= vclpc AFTER T + 16 ns;
oldtakt:=t;
END PROCESS;
END behaviour;
Last edited:
And the second half of the code.
Code:
-- VHDL-Beschreibung des Speicherbausteins (RAM)
ENTITY RAM IS
GENERIC(T : Time := 2ns);
PORT(admux, write : IN integer;
datin : IN ltg;
datout : OUT ltg);
END RAM;
ARCHITECTURE behaviour OF RAM IS
BEGIN
PROCESS
TYPE word IS ARRAY (1 TO 25) OF integer;
VARIABLE opwort, adwort : word;
VARIABLE oldwrite, oldadresse, adresse : integer;
VARIABLE start, vadrout, vopcout : integer;
BEGIN
IF start=0 THEN
opwort(1):=1;
adwort(1):=12;
opwort(2):=12;
adwort(2):=15;
opwort(3):=1;
adwort(3):=15;
opwort(4):=10;
adwort(4):=0;
opwort(5):=2;
adwort(5):=16;
opwort(6):=12;
adwort(6):=15;
opwort(7):=1;
adwort(7):=12;
opwort(8):=3;
adwort(8):=13;
opwort(9):=12;
adwort(9):=14;
opwort(10):=11;
adwort(10):=0;
opwort(11):=2;
adwort(11):=3;
opwort(12):=0;
adwort(12):=2;
opwort(13):=0;
adwort(13):=2;
start:=1;
END IF;
adresse:=admux;
IF write=1 AND oldwrite=0 THEN
opwort(adresse):=datin(1);
adwort(adresse):=datin(2);
END IF;
IF adresse/=oldadresse THEN
vopcout:=opwort(adresse);
vadrout:=adwort(adresse);
END IF;
datout(1) <= vopcout AFTER T;
datout(2) <= vadrout AFTER T;
oldwrite:=write;
oldadresse:=adresse;
END PROCESS;
END behaviour;
-- VHDL-Beschreibung des Taktgenerators (clock)
ENTITY clock IS
GENERIC(T : Time := 60ns);
PORT(beat : OUT integer);
END clock;
ARCHITECTURE behaviour OF Clock IS
BEGIN
PROCESS
variable oldtakt : integer;
BEGIN
IF oldtakt=1 THEN
beat <= 0 AFTER T/2;
ELSE
beat <= 1 AFTER T/2;
END IF;
oldtakt := beat;
END PROCESS;
END behaviour;
-- Strukturmodell des gesamten Rechners "TOY"
ENTITY TOY IS
END TOY;
ARCHITECTURE structure OF TOY IS
SIGNAL OPCONIR, ADIR, ACUNFL, ADPCMUX, ADMUXRAM, CONCL, CLIR,
WRITERAM, : integer;
SIGNAL ALUOUT, ALUCON, RAMOUT, MUXCON, CLOCKPC : ltg;
COMPONENT ALUaccu
GENERIC(T : Time := 4 ns);
PORT(ramdat, alucon : IN ltg;
nullflag : OUT integer; aluout : OUT ltg);
END COMPONENT;
COMPONENT Mux
GENERIC(T : Time := 2ns);
PORT(ir, pc : IN integer; addrir : IN ltg;
adout : OUT integer);
END COMPONENT;
COMPONENT PC
GENERIC(T : Time := 4ns);
PORT(iri, nflag : IN integer; clock: IN ltg;
outa : OUT integer);
END COMPONENT;
COMPONENT IR
GENERIC(T : Time := 4ns);
PORT(clockir : IN integer; ramin : IN ltg;
opcn, adpc : OUT integer);
END COMPONENT;
COMPONENT RAM
GENERIC(T : Time := 2ns);
PORT(admux, write : IN integer; datin : IN ltg;
datout : OUT ltg);
END COMPONENT;
COMPONENT Control
GENERIC(T : Time := 2ns);
PORT(opco, takt : IN integer;
clir, wriram : OUT integer;
alcon, adir, clpc : OUT ltg);
END COMPONENT;
COMPONENT Clock
GENERIC(T : Time := 60ns);
PORT(beat : OUT integer);
END COMPONENT;
BEGIN
ALUaccu : ALUaccu
PORT MAP(ramdat=>RAMOUT, nullflag=>ACUNFL,
aluout=>ALUOUT, alucon=>ALUCON);
END ALUaccu;
RAM : RAM
PORT MAP(datin=>ALUOUT, admux=>ADMUXRAM,
write=>WRITERAM, datout=>RAMOUT);
END RAM;
IR : IR
PORT MAP(ramin=>RAMOUT, clockir=>CLIR,
opcn=>OPCONIR, adpc=>ADIR);
END IR;
PC : PC
PORT MAP(iri=>ADIR, clock=>CLOCKPC,
nflag=>ACUNFL, outa=>ADPCMUX);
END PC;
Mux : Mux
PORT MAP(ir=>ADIR, pc=>ADPCMUX, addrir=>MUXCON,
adout=>ADMUXRAM);
END Mux;
Control : Control
PORT MAP(opco=>OPCONIR, takt=>CONCL, clir=>CLIR,
alcon=>ALUCON, adir=>MUXCON, clpc=>CLOCKPC,
wriram=>WRITERAM);
END Control;
Clock : Clock
PORT MAP(beat => CONCL);
END Clock;
END structure;Thank you to post this link but still I don't understand . I don't know what I do ? I am searching for Instruction decoder from last 6 hours. But I am not getting anything
I am feeling irritating
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