# Processing/Sampling IF(IQ) signals

Discussion in 'General Electronics Chat' started by himadri117, Nov 11, 2014.

Nov 11, 2014
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Signal Characteristics: The IF (I/Q) signal consists of a DC component and an AC component.

DC Component: 2.52V; AC Component: 1.72 – 2.04 V (V P-P); BW: 20Hz - 500kHz; Power: 20dB

Requirement: Now I want to digitize this signal for further processing. I prefer a sampling at 1 MSPS with ADC and then porting digital data to PC using a FPGA over SPI interface.

Problem: The problem is, the signal with DC and AC component ranges from 3.5V to -1.5V with 2.5V from DC and almost 1V from positive cycle or negative cycle of the AC signal. Now I can use a coupled capacitor to block the Dcand use the AC for processing. My choice of ADC reference voltage is almost 2V-2.5V (for good resolution usability of ADC) so the signal can be amplified. But this signal have a negative part which I think is not good for a linear behavious for the ADC, as it has no negative reference voltage level. ADC reference is from 1V-5V. Using a rectifier is not a good choice from my view.

Question: How can I digitize this signal? Also comment on my views if not correct as I have only theoretical knowledge and never worked on a practical project.

2. ### alfacliff Well-Known Member

Dec 13, 2013
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428
I Q signals are in quadrature, 90 degree phase shifted, not one rf and one dc. with a 90 degree phase shift, you can mathematcly detect many modes of modulation.

Nov 11, 2014
10
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Thanx for the reply. I know the I and Q signals are 90 deg phase shifted. I didn't mean one as DC and other as RF. Each I or Q channel has a DC and RF part.... For eg. if i take only theI channel I have the RF of 2V peak to peak and DC part of 2.5V. Now i want to digitize this signal.

4. ### MrChips Moderator

Oct 2, 2009
12,623
3,451
Add a DC voltage bias to bring the signal to the mid-range of the ADC input.