problem with reading from ram

Discussion in 'Embedded Systems and Microcontrollers' started by maia31, Jul 23, 2011.

  1. maia31

    Thread Starter New Member

    Jul 20, 2011
    well if i want send 200 bite per second from ram in to fpga
    and my ram is 128
    what should i do?
    i want do it with vhdl
    and if any one can give me a sample program i appreciate
    and my ram need refresh each 3.9 micro second
    and i work with memory controller
    and my ram is ddr2 sdram
    and i hope i explain it good
    and by the way this s my first project
  2. royalvasudeva

    New Member

    Jun 17, 2011
    How send byte data using c program pls explain me
  3. maia31

    Thread Starter New Member

    Jul 20, 2011
    send to what?
    end from what?
    c or you mean verilog?
  4. PCB_designer

    New Member

    Jul 28, 2011
    Some (or all) ddr2 sdram may not work as slow as micro seconds. The refresh alone may have to be generated repeatedly at significantly faster intervals than that.

    You can learn how to use ddr2 sdram by studying the data sheets of several different ICs. They will have the most information, especially if they have lots of timing information and waveforms.

    Here's a random one to start, for me, this has enough information to get started:

    This one may be harder to learn with since it has fewer timing waveforms: Sheets/Qimonda PDFs/HYB18T512xx0BF.pdf

    I only provided the second link so you can get an idea what kinds of datasheets you probably won't learn well with; so you can skip it until you've gotten better.

    Good luck with your project.
  5. guitarguy12387

    Active Member

    Apr 10, 2008
    This is going to be a beastly project. Interfacing to DDR SDRAM is NOT easy. Mr. PCB has the right approach... you basically need to look at the timing diagrams and implement that.

    This is not a good 'first project' for anyone. If you insist, i'd suggest learning up on IP to do the job. Just interfacing with an IP core will be non-trivial in itself. You never specified your hardware platform... but Xilinx offers the Memory Interface Generator (MIG) IP core which will generate the interface and controller for you. However, you will still need to do a lot of reading to know how to properly configure the core and interface to it.