problem with monostable 555 circuit

Discussion in 'General Electronics Chat' started by aditya.rajgaria, Feb 10, 2010.

  1. aditya.rajgaria

    Thread Starter New Member

    Feb 10, 2010
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    hi...i wanted to ask that i have been experiencing a problem with the capacitor discharging while using monostable...

    as the theory goes the charging of capacitor starts for the -ve edge of the trigger and then when it reaches 2/3 vcc the capacitor completely is charged and till then the output is higher, irrespective of the input.

    but i m unable to understand why in my design the capacitor discharging depending on the input signal...it perfectly starts charging the the -ve edge of the signal but is discharged irrespective of its charged value during the +ve edge of the input....

    i have tried changing the time constant but this doesn't help....

    please reply..
     
  2. bertus

    Administrator

    Apr 5, 2008
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    Greetings! And welcome to AAC!

    I've moved your post into its own thread, where it will draw more responses:
    http://forum.allaboutcircuits.com/showthread.php?t=14018

    This is a special thread of Bill Marsden for the eBook.

    Please refrain from "hijacking" existing threads with tangent or off-topic questions. You can create new threads for new questions using the "New Thread" button on the upper left of the page.

    Greetings,
    Bertus
     
  3. Wendy

    Moderator

    Mar 24, 2008
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    Show us your schematic, we'll be glad to help.
     
  4. aditya.rajgaria

    Thread Starter New Member

    Feb 10, 2010
    11
    0
    today only i got a thing that when the input duty cycle was more than 25%
    then only the monostable was working like it should be...else the output waveforms were like the one i have shown in the diagram....

    as u can see...what ever be the T = RC, the capacitor remained charged till the input is low...although when I increased the value of C too high, capacitor missed one input pulse bt operated in the same manner as above..

    so please explain why this 25% duty cycle contraint is there and how to over come that..!!
     
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  5. MikeML

    AAC Fanatic!

    Oct 2, 2009
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    Differentiate the trigger with a series C, R pullup to Vdd.
     
  6. aditya.rajgaria

    Thread Starter New Member

    Feb 10, 2010
    11
    0
    ok i'll see that but why is this problem coming at all....??
     
  7. MikeML

    AAC Fanatic!

    Oct 2, 2009
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    If the trigger pulse persists beyond the RC time constant, then the 555 never times out, and the output stays high until the trigger goes high again.
     
  8. Wendy

    Moderator

    Mar 24, 2008
    20,765
    2,536
    R1 and C1 is needed in this design.

    [​IMG]

    If your logic is normally high, going to low and back to high to trigger the monostable R1 and C1 are not needed, but normally they are required.

    In the design shown at 555 Monostable they are also there, for a reason.

    Pin 2 must be high when the timer is idle. This is not optional.
     
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