problem with CCP3 of PIC18F46K22

Discussion in 'Embedded Systems and Microcontrollers' started by jean120, Apr 28, 2016.

  1. jean120

    Thread Starter Member

    Jan 24, 2016
    75
    1
    Hello,I am asking myself why my codes here below are not working
    movlw 0x0C
    movwf CCP1CON ;CCP1 and CCP2 configured to PWM
    movwf CCP2CON
    movwf CCP3CON

    with MPLAB SIM,I found that the value 0X0C is not passing to the CCP3CON with this PIC what might be the mistake here?

    Thanks and Best Regards,
     
  2. dannyf

    Well-Known Member

    Sep 13, 2015
    1,769
    358
    Do you have the same problem with 1 and 2?

    How do you know that you have a problem with 3?
     
  3. MaxHeadRoom

    Expert

    Jul 18, 2013
    10,507
    2,367
    The CCP1,2,3CON all have identical assignments?
    What do you see in CCP3CON?
    Max.
     
  4. nickelflipper

    Active Member

    Jun 2, 2010
    280
    35
    CCP3CON is outside the normal 256 byte range of the SFR's with the PIC18fx6k22 devices. Use BSR to access the bank?, or I believe MPLAB would accept a "banksel CCP3CON" to access the register. Same goes for a whole host of other registers affecting the TMRx, PRx, etc.
     
  5. jean120

    Thread Starter Member

    Jan 24, 2016
    75
    1
    Hello,I used the BANKSEL and it solved my problem,now a new issue is that when programming my PIC18F46K22 with ICD3,I get the 3 PWM Signals on CCP1,CCP2 and CCP3 as required but when taking the PIC into my soldered board of circuit I don`t get the signals,no any,could you suggest the way for solving this?

    Please help.
     
  6. MaxHeadRoom

    Expert

    Jul 18, 2013
    10,507
    2,367
    Have you a suitable pull up resistor on the MCLR?
    Max.
     
  7. jean120

    Thread Starter Member

    Jan 24, 2016
    75
    1
    Yes Sir,a pull up resistor is there well of 10Kohm.
    additionally to my previous post #5 when I tried to measure the continuity on the board I found that the Quartz is connected on pin 15 and 16 of the PIC.whereas on the board I soldered the quartz is on pin 13a and 14

    Please help
     
  8. MaxHeadRoom

    Expert

    Jul 18, 2013
    10,507
    2,367
    13 & 15 are your Sys ext clock Xtal.
    15 & 16 are SOSCO 32.768Khz secondary oscillator.
    Max.
     
  9. jean120

    Thread Starter Member

    Jan 24, 2016
    75
    1
    I hope so as you stated above but I am asking myself why the quartz connected on 13&14 (not 15 as you stated above) is not allowing the PIC to operate and give me the needed signals.

    When the PIC is in the ICD 3 I get the three PWM Signals but the one of CCP3_RB5 is low comparing to others (I think the reason is because the pins 15&16 where CCP1 and CCP2 are give the PWM signals),when my PIC is on the soldered board nothing obtained with Quartz on the pins 13&14.

    Please help!!
     
  10. MaxHeadRoom

    Expert

    Jul 18, 2013
    10,507
    2,367
    What is your CONFIG setting for FOSC oscillator?
    Max.
     
  11. jean120

    Thread Starter Member

    Jan 24, 2016
    75
    1
    My configurations bits are the following:

    CONFIG FOSC = RCIO6
    CONFIG EBTR3 = OFF
    CONFIG PLLCFG = ON
    CONFIG CCP3MX = PORTB5
    I am using the external resonator (Quartz of 20MHZ)connected on pin 13&14 of the PIC
    Please help
     
    Last edited: May 3, 2016
  12. MaxHeadRoom

    Expert

    Jul 18, 2013
    10,507
    2,367
    Look up means of system clock p.33 etc , you have external RC Osc, read up on the LP,XT HS methods.
    Max.
     
  13. jean120

    Thread Starter Member

    Jan 24, 2016
    75
    1
    What should be the best configuration bits in my case so the system could work effectively?
    Please help!!
     
  14. MaxHeadRoom

    Expert

    Jul 18, 2013
    10,507
    2,367
    What Xtal do you have on p13 & p14?
    Max.
     
  15. jean120

    Thread Starter Member

    Jan 24, 2016
    75
    1
    Hi,I have Xtal of 20MHZ,
    Best Regards,
     
  16. MaxHeadRoom

    Expert

    Jul 18, 2013
    10,507
    2,367
    CONFIG FOSC = HSHP
    Max.
     
  17. jean120

    Thread Starter Member

    Jan 24, 2016
    75
    1
    Sir,is that parameter enough so that I can get the signal on my respective CCP1,CCP2 and CCP3 as planned?I mean on my soldered board.

    Best Regards
     
  18. jean120

    Thread Starter Member

    Jan 24, 2016
    75
    1
    The following are my configuration bits extracted from MPLAB X but still I have a problem

    ; CONFIG1H
    CONFIG FOSC = HSMP ; Oscillator Selection bits (HS oscillator (medium power 4-16 MHz))
    CONFIG PLLCFG = OFF ; 4X PLL Enable (Oscillator used directly)
    CONFIG PRICLKEN = ON ; Primary clock enable bit (Primary clock is always enabled)
    CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
    CONFIG IESO = ON ; Internal/External Oscillator Switchover bit (Oscillator Switchover mode enabled)

    ; CONFIG2L
    CONFIG PWRTEN = OFF ; Power-up Timer Enable bit (Power up timer disabled)
    CONFIG BOREN = SBORDIS ; Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
    CONFIG BORV = 190 ; Brown Out Reset Voltage bits (VBOR set to 1.90 V nominal)

    ; CONFIG2H
    CONFIG WDTEN = OFF ; Watchdog Timer Enable bits (Watch dog timer is always disabled. SWDTEN has no effect.)
    CONFIG WDTPS = 32768 ; Watchdog Timer Postscale Select bits (1:32768)

    ; CONFIG3H
    CONFIG CCP2MX = PORTC1 ; CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
    CONFIG PBADEN = OFF ; PORTB A/D Enable bit (PORTB<5:0> pins are configured as digital I/O on Reset)
    CONFIG CCP3MX = PORTB5 ; P3A/CCP3 Mux bit (P3A/CCP3 input/output is multiplexed with RB5)
    CONFIG HFOFST = OFF ; HFINTOSC Fast Start-up (HFINTOSC output and ready status are delayed by the oscillator stable status)
    CONFIG T3CMX = PORTC0 ; Timer3 Clock input mux bit (T3CKI is on RC0)
    CONFIG P2BMX = PORTD2 ; ECCP2 B output mux bit (P2B is on RD2)
    CONFIG MCLRE = EXTMCLR ; MCLR Pin Enable bit (MCLR pin enabled, RE3 input pin disabled)

    ; CONFIG4L
    CONFIG STVREN = ON ; Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
    CONFIG LVP = ON ; Single-Supply ICSP Enable bit (Single-Supply ICSP enabled if MCLRE is also 1)
    CONFIG XINST = OFF ; Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

    ; CONFIG5L
    CONFIG CP0 = OFF ; Code Protection Block 0 (Block 0 (000800-003FFFh) not code-protected)
    CONFIG CP1 = OFF ; Code Protection Block 1 (Block 1 (004000-007FFFh) not code-protected)
    CONFIG CP2 = OFF ; Code Protection Block 2 (Block 2 (008000-00BFFFh) not code-protected)
    CONFIG CP3 = OFF ; Code Protection Block 3 (Block 3 (00C000-00FFFFh) not code-protected)

    ; CONFIG5H
    CONFIG CPB = OFF ; Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
    CONFIG CPD = OFF ; Data EEPROM Code Protection bit (Data EEPROM not code-protected)

    ; CONFIG6L
    CONFIG WRT0 = OFF ; Write Protection Block 0 (Block 0 (000800-003FFFh) not write-protected)
    CONFIG WRT1 = OFF ; Write Protection Block 1 (Block 1 (004000-007FFFh) not write-protected)
    CONFIG WRT2 = OFF ; Write Protection Block 2 (Block 2 (008000-00BFFFh) not write-protected)
    CONFIG WRT3 = OFF ; Write Protection Block 3 (Block 3 (00C000-00FFFFh) not write-protected)

    ; CONFIG6H
    CONFIG WRTC = OFF ; Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
    CONFIG WRTB = OFF ; Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
    CONFIG WRTD = OFF ; Data EEPROM Write Protection bit (Data EEPROM not write-protected)

    ; CONFIG7L
    CONFIG EBTR0 = OFF ; Table Read Protection Block 0 (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)
    CONFIG EBTR1 = OFF ; Table Read Protection Block 1 (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)
    CONFIG EBTR2 = OFF ; Table Read Protection Block 2 (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)
    CONFIG EBTR3 = OFF ; Table Read Protection Block 3 (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)

    ; CONFIG7H
    CONFIG EBTRB = OFF ; Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)





    For solving the problem I remove the PIC from the ICD3 and connected on the breadboard where the pins (PGD,PGC,MCLR,VDD and VSS)are connected with extension wires to the breadboard but now the pic can be detected by MPLAB IDE it is saying

    ICD3Err0086: Target Device ID (00000000) does not match
    expected Device ID (00005400). If you experience persistent
    problems communicating, the ICD 3 test interface can be
    used to help diagnose the problem.


    Please could you help me to find a solution?


    Best Regards
     
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