Problem: Transmitting Between Two Shift Registers

Discussion in 'Homework Help' started by Ryan_1700, Apr 13, 2009.

  1. Ryan_1700

    Thread Starter New Member

    Apr 13, 2009
    2
    0
    We are asked to do the following (we are designing this circuit using the Logic Works program):

    Connect two 8-bit shift registers to perform shift operations in the following steps:

    1. Load shift register 1 with the parallel code 10110101.

    2. Convert the parallel code in shift register 1 into a serial code with the MSB (most significant bit) going first, and transmit the serial code into shift register 2 until the latter receives the entire code in a reverse order, i.e., 10101101, while the code in shift register 1 is unchanged and maintained as 10110101. Hand in the circuit diagram and the waveforms of the clock and the serial code signals transmitted between the two registers.


    A screenshot of the circuit I have designed thus far can be found here: http://img26.imageshack.us/img26/5859/shiftregisterscircuitdi.png

    The inputs and clocks have the following parameters:

    the clock for load for shift register 1 has a low-time of 10 and a high-time of 160 (the idea is that it is initially 0 to load the parallel code, and then once it is loaded, load should be 1 from that point on so that shift register 1 just continuously shifts the 8-bit number)

    The clocks for both shift register 1 and shift register 2 have a low and high time of 5.

    As can be seen on the circuit diagram, the output of Q7 (i.e., reg1 MSB signal line) is connected to SI for shift register 1 so that once something is shifted out it is then shifted back in to the LSB of shift register 1. The output of Q7 (reg1 MSB signal line) is also connected to SI for shift register 2 so that the 8-bit number can be received in the reverse order for shift register 2 (i.e., the first bit shifted out of shift register 1 goes to the LSB of shift register 2 and so on and so forth).


    The waveform for the reg1 MSB signal line is correct, as when the parallel code is first loaded it has a value of 1, then after the first shift it has a value of 0 (and the 1 that was the MSB is shifted out and then goes to the LSB), and then after the second shift it has a value of 1, and so on and so forth, following the code sequence of 10110101, as it should. However, the waveform for the reg2 MSB signal line is not producing the correct result (i.e.,10101101), but I am not sure why this is the case. I felt like the way I designed the circuit is the logical (and correct) way to go about designing this circuit, so if there are any noticeable issues/problems with my design that would explain why I am getting incorrect results for the reg2 MSB signal line, I would certainly appreciate it if they could be brought to my attention, as I am fairly new to designing circuits.
     
  2. RiJoRI

    Well-Known Member

    Aug 15, 2007
    536
    26
    First, it is not clear if both shift registers are using the same clock.
    Second, does reg2 have some way of controlling which way the shift is done?
    Third, if reg2 also has a LD control, it should be tied inactive to keep from getting random loads of garbage.
    Finally, does reg2 have some way of controlling which way the shift is done? <-- very important point!

    --Rich
     
  3. Ryan_1700

    Thread Starter New Member

    Apr 13, 2009
    2
    0
    *The two shift registers are using different clocks, but both clocks have the same high-time/low-time (5/5).

    *This is something I thought about and it may be an issue, but I believe in Logic Works when you use a serial-in shift register the first bit it receives goes to the LSB (Q0 in this case since it's an 8-bit shift register), the next bit goes to the second-to-last LSB (i.e., Q1), and so on until the eight bit would go to Q7 (the MSB). Then once everything is received, I thought it would just shift like shift register 1 does, but maybe there is an issue either with how the original sequence is received by shift register 2 and/or an issue with the shifting process itself in shift register 2. Do you have any further insight on this point?

    *I used a serial-in shift register for shift register 2 (whereas a parallel-in was used for shift register 1); this device does not have a LD control, as it only has the clock and SI (shift input) as its two inputs.
     
  4. RiJoRI

    Well-Known Member

    Aug 15, 2007
    536
    26
    The two shift registers are using different clocks, but both clocks have the same high-time/low-time (5/5).

    And what happens if the two clocks are 180* out of phase? Different clocks WILL drift -- Murphy's Law.

    And is there an output enable on reg2? If not, you'll need to add a latch and perhaps a counter to control it, otherwise you'll never know when the shifting is done; more importantly, any other devices attached to reg2 will see spurious signals.

    --Rich
     
  5. PRS

    Well-Known Member

    Aug 24, 2008
    989
    35
    This reminds me of a project I did in lab while in college. But we had to send our data via infrared. My partner built the xmitter, I built the receiver. We obviously had to use 2 clocks. I think this is pretty much the same problem as yours.

    I don't remember the solution about synchronizing clocks. Serial Ports use a sequence of data to reset the clock. Since your code starts with 1 just have that first pulse start the second shift register's clock.

    To keep the first clock from shifting out its shift register's useful data byte, use the last bit to disable its clock before it loses any of the code. Do the same to stop the second shift register.
     
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