problem in single supply op amp simulation

Discussion in 'General Electronics Chat' started by spidermanIIII, Mar 29, 2015.

  1. spidermanIIII

    Thread Starter Member

    Nov 22, 2013
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    hello, we asked to simulate this signal conditioning examples in Proteus the example is case 3 and case 4 the problem when i put the input which is negative the out put is always 5 volt please i need help to simulate the case 3 and 4 examples in pdf file what is the wrong in my simulation
     
  2. wayneh

    Expert

    Sep 9, 2010
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    Can the op-amp you are using sense voltages as close to the power rails as in the TI examples? I suspect you are operating outside the common-mode range.
     
  3. crutschow

    Expert

    Mar 14, 2008
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    Please post as standard graphic or pdf files.
    I cannot read the Proteus files.
     
  4. spidermanIIII

    Thread Starter Member

    Nov 22, 2013
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  5. MikeML

    AAC Fanatic!

    Oct 2, 2009
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    What is the RG thing in the upper left corner. Is it a voltage source, or a probe to show the voltage there?
     
  6. spidermanIIII

    Thread Starter Member

    Nov 22, 2013
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    it is a voltage source
     
  7. MikeML

    AAC Fanatic!

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    Looking at case 3: What is the voltage at the + (non-inverting) input?

    What is the allowed input common-mode range for this amplifier when it is operated from 0V and 10V?

    Why is the ratio of R1 to R2 what it is?
     
  8. MikeML

    AAC Fanatic!

    Oct 2, 2009
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    Looking at case 4: The voltage at the + (non-inverting) input is zero tied to ground.

    What is the allowed input common-mode range for this amplifier when it is operated from 0V and 10V?

    Considering that the output swing of the LM324 is from near oV to 10V-1.5V = 8.5V, and that the current injected by R1, R2 from the 5V bias source is tiny, what is the allowed input range from RG2 that would keep the opamp in its linear region (simple algebra, you dont need a simulator)?
     
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