Problem in Non restoring Division in VHDL

Discussion in 'Programmer's Corner' started by Raj11188, Jun 14, 2013.

  1. Raj11188

    Thread Starter New Member

    Jun 14, 2013
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    0
    I was writing my code for non restoring division algorithm in VHDL and experiencing some problem, in the code I have written 16 bit division, but while doing synthesis waveform I didn't get the correct result code is shown below:

    Code ( (Unknown Language)):
    1.  
    2. library IEEE;
    3. use IEEE.STD_LOGIC_1164.ALL;
    4. use IEEE.STD_LOGIC_ARITH.ALL;
    5. use IEEE.STD_LOGIC_UNSIGNED.ALL;
    6.  
    7. entity division is
    8. Port ( q : in STD_LOGIC_VECTOR (15 downto 0);
    9. m : in STD_LOGIC_VECTOR (15 downto 0);
    10. qf : out STD_LOGIC_VECTOR (15 downto 0);
    11. rf : out STD_LOGIC_VECTOR (15 downto 0);
    12. clk:in std_logic;
    13. rst:in std_logic);
    14. end division;
    15. architecture Behavioral of division is
    16. signal aq,m_sub,m_add:STD_LOGIC_VECTOR (32 downto 0);
    17. signal m_neg: STD_LOGIC_VECTOR (16 downto 0);
    18. signal count:std_logic_vector(4 downto 0);
    19. begin
    20. m_neg<=(not('0'&m))+1;
    21. process(clk,rst,m)
    22. begin
    23. if(rst='1') then
    24. count<="00000";
    25. aq<="00000000000000000"&q;
    26. m_add<='0'&m&"0000000000000000";
    27. m_sum<=m_neg&"0000000000000000";
    28. elsif rising_edge(clk) then
    29. count<= count+"00001";
    30. if(count<="1111") then
    31. aq<=aq(31 downto 0)&'0';
    32. if(aq(32)='1') then
    33. aq<=aq+m_add;
    34. else
    35. aq<=aq+m_sub;
    36. end if;
    37. aq(0)<= not(aq(32));
    38. elsif(count="10000") then
    39. if(aq(32)='1') then
    40. aq<=aq+m_sum;
    41. else
    42. aq<=aq+m_sub;
    43. end if;
    44. else
    45. aq<=aq;
    46. end if;
    47. end if;
    48.  
    49. qf<=aq(15 downto 0);
    50. rf<=aq(31 downto 16);
    51. end process;
    52. end Behavioral;
    53.  
     
    Last edited by a moderator: Jun 16, 2013
  2. WBahn

    Moderator

    Mar 31, 2012
    17,715
    4,788
    How about showing some test waveforms comparing what you applied, what you got, and what you consider to be the correct waveform that you were expecting to see?
     
  3. Raj11188

    Thread Starter New Member

    Jun 14, 2013
    5
    0
    Code ( (Unknown Language)):
    1.  
    2. ---------------------------------------------------
    3. LIBRARY ieee;
    4. USE ieee.std_logic_1164.ALL;
    5. USE ieee.std_logic_unsigned.all;
    6. USE ieee.numeric_std.ALL;
    7. ENTITY vtest_vhd IS
    8. END vtest_vhd;
    9. ARCHITECTURE behavior OF vtest_vhd IS
    10.  -- Component Declaration for the Unit Under Test (UUT)
    11.  COMPONENT division
    12.  PORT(
    13.   q : IN std_logic_vector(15 downto 0);
    14.   m : IN std_logic_vector(15 downto 0);
    15.   clk : IN std_logic;
    16.   rst : IN std_logic;          
    17.   qf : OUT std_logic_vector(15 downto 0);
    18.   rf : OUT std_logic_vector(15 downto 0)
    19.   );
    20.  END COMPONENT;
    21.  --Inputs
    22.  SIGNAL clk :  std_logic := '0';
    23.  SIGNAL rst :  std_logic := '0';
    24.  SIGNAL q :  std_logic_vector(15 downto 0) := (others=>'0');
    25.  SIGNAL m :  std_logic_vector(15 downto 0) := (others=>'0');
    26.  --Outputs
    27.  SIGNAL qf :  std_logic_vector(15 downto 0);
    28.  SIGNAL rf :  std_logic_vector(15 downto 0);
    29. BEGIN
    30.  -- Instantiate the Unit Under Test (UUT)
    31.  uut: division PORT MAP(
    32.   q => q,
    33.   m => m,
    34.   qf => qf,
    35.   rf => rf,
    36.   clk => clk,
    37.   rst => rst
    38.  );
    39.  tb : PROCESS
    40.  BEGIN
    41.   -- Wait 100 ns for global reset to finish
    42.   wait for 100 ns;
    43.  
    44. rst<='1';
    45. wait for 100 ns;
    46. rst<='0';
    47. q<=x"0008";
    48. m<=x"0003";  -- Place stimulus here
    49.  
    50.   wait; -- will wait forever
    51.  END PROCESS;
    52. process
    53. begin
    54. clk<='0';
    55. wait for 5 ns;
    56. clk<='1';
    57. wait for 5 ns;
    58. end process;
    59.  
    60. END;
    61.  
     
    Last edited by a moderator: Jun 16, 2013
  4. Raj11188

    Thread Starter New Member

    Jun 14, 2013
    5
    0
    Above code is for division of 8 by 3, and below I've shown waveform where;
    m_reen > m_add
    m_dhan > m_sum

    Sir pls provide me ure email id, there is a problem posting image file on this website
    :( :(
     
  5. WBahn

    Moderator

    Mar 31, 2012
    17,715
    4,788
    Everyone else posts image files all the time. Be sure you are following the guidelines for posting image files.

    And, no, I most certainly will NOT provide you with my e-mail address.
     
  6. Raj11188

    Thread Starter New Member

    Jun 14, 2013
    5
    0
  7. Raj11188

    Thread Starter New Member

    Jun 14, 2013
    5
    0
    I am performing here division of 8 by 3. And result should be 2 remainder and 2 quotient, whereas in the test bench waveform I've got something wrong.
    here "qf" is final quotient and "rf" is final remainder in which result is kept
     
  8. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    What is your division algorithm supposed to be doing? I see lots of shifting and adding, but not familiar with that method. Also hard to read your code w/o indentations.
     
  9. WBahn

    Moderator

    Mar 31, 2012
    17,715
    4,788
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