problem in fpga program

Discussion in 'Embedded Systems and Microcontrollers' started by vinay arora, Jun 24, 2011.

  1. vinay arora

    Thread Starter New Member

    Jun 3, 2011
    15
    0
    I am not able to understand that how it generate a 440 hz from the 2 program shown below, with 50% duty cycle.




    "A" note (440Hz)

    Ok, better than a random frequency, why not try to get a 440Hz signal. That's the frequency of the "A" note.

    Instead of dividing 25MHz by 65536, we need to divide by 56818. Here we go.

    module music(clk, speaker);
    input clk;
    output speaker;

    reg [15:0] counter;
    always @(posedge clk) if(counter==56817) counter <= 0; else counter <= counter+1;

    assign speaker = counter[15];
    endmodule

    There is a problem though. The frequency is 440Hz, as expected, but the output duty cycle is not 50% anymore. The low level goes from counter=0 to counter=32767 (when bit 15 of counter is low) and then high level from 32768 to 56817. That gives us "speaker" being high only 42% of the time.

    The easiest way to get a 50% duty cycle is to add a stage that divides the output by 2. So first we divide by 28409 (instead of 56818) and then by 2.

    module music(clk, speaker);
    input clk;
    output speaker;

    reg [14:0] counter;
    always @(posedge clk) if(counter==28408) counter <= 0; else counter <= counter+1;

    reg speaker;
    always @(posedge clk) if(counter==28408) speaker <= ~speaker;
    endmodule
     
  2. jmdejoanelli

    New Member

    Mar 13, 2011
    10
    1
    is that verilog or vhdl?
     
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