problem cascaded jk flip flops

Discussion in 'General Electronics Chat' started by Nathan Hale, Nov 24, 2013.

  1. Nathan Hale

    Thread Starter Active Member

    Oct 28, 2011
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    Hello guys ! I am back again!...with a problem again....so i cascaded 2 jk flip flops (7407) so that i can make a 4 bit counter. The wiring is correct but the 7 seg display is ...well...just showing up weird characters. any ideas what i might be doing wrong? are there any precautions that i need to take while cascading flip flops?

    thank you for ur replies.

    p.s. the ground (black) wire from the frequency generator goes into the last flip flops ground ( pin 7 ) right ?


    Untitled.png
    [​IMG]
     
  2. BillB3857

    Senior Member

    Feb 28, 2009
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    How do you have the 7 segment display connected to the JKs? What kind of display are you expecting to see? What kind of counter do cascaded JKs produce?
     
  3. WBahn

    Moderator

    Mar 31, 2012
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    Your second image, which I am hoping is a schematic, is not showing up.

    Do you mean you are taking 4 JK FFs (two each from two dual-JKFF packages) to make a 4-bit counter?
     
  4. Nathan Hale

    Thread Starter Active Member

    Oct 28, 2011
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    How do you have the 7 segment display connected to the JKs? What kind of display are you expecting to see? What kind of counter do cascaded JKs produce?
    Firstly let me tell you that i have 2 "7407" jk flip flops. Each IC has 2 flip flops inside.
    Well I have the "Q" of each flip flop going into the "A,B,C,D" inputs of a 7447 BCD to 7 seg decoder. I am expecting to see a down count starting from 9 to 0 and then going back to 9. I dont know know what kind of counter cascaded JKs produce. maybe someone here can tell me.

    Your second image, which I am hoping is a schematic, is not showing up.
    There is only one image in my post. It is a block diagram of the jk i am using.
    Do you mean you are taking 4 JK FFs (two each from two dual-JKFF packages) to make a 4-bit counter?

    Yes sir. I have 2 ICs. The "Q'" from the "second FF" ( pin 6 IC # 1 ) is being fed into the clock of the "third" FF (pin 12 IC # 2). The rest is just regular wiring.

    The data sheet for the FF is below.
    https://www.jameco.com/Jameco/Products/ProdDS/49234.pdf
     
  5. shteii01

    AAC Fanatic!

    Feb 19, 2010
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    7447 has four inputs: A, B, C, D. Each input is a bit. So 7447 is 4-bit. 2^4=16. That means that 7447 will show 16 values, not 9. 7447 will show 0-9 for first ten values, then instead of 10 you will see letter A, instead of 11 you will B, instead of 12 it will show C, and so on, instead of 15 it will show F. Total of 16 values.

    To do 0-9 then back to 0 again you will need some extra circuitry.

    Same is true in reverse. You want to start at 9 and count to 0. Normally operated 7447 will start at F and count to 0.
     
  6. Nathan Hale

    Thread Starter Active Member

    Oct 28, 2011
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    My issue is when i turn on the circuit and the clock all i am getting on the display is weird LED combinations. When i took out the second IC and used only on IC as a 3 bit counter , it counts down nicely from 3 to 2 to 1 to 0 and back to 3 again. nothing like that is happening when i hook up the 2nd IC. All i get is weird stuff like the LED A,F,C being on or C,E,G being on.
     
  7. shteii01

    AAC Fanatic!

    Feb 19, 2010
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    Time to post schematic.
     
  8. BillB3857

    Senior Member

    Feb 28, 2009
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    JK flip flops can be configured in many different ways. As an example, if J and K are both tied high, a clock pulse on the clock input will toggle the state. Also, if you are expecting to see numbers from the display you will need a BCD to 7 segment decoder/driver.
     
  9. MrChips

    Moderator

    Oct 2, 2009
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    7407 is a hex open-collector buffer.
    You must mean a 74107 dual J-K flip-flop.
     
  10. absf

    Senior Member

    Dec 29, 2010
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    Is this the pattern you're getting from the count of 10 to 14?
     
  11. WBahn

    Moderator

    Mar 31, 2012
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    What do you mean by "regular wiring"? We are NOT mind readers. Show us a schematic of how you have wired these two chips. You have given NO indication of how you have wired any of the J or the K inputs, only that you are venturing into the world of asynchronous logic by using gated-clocks.
     
  12. WBahn

    Moderator

    Mar 31, 2012
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    Would you PLEASE show a schematic?!?!
     
  13. Nathan Hale

    Thread Starter Active Member

    Oct 28, 2011
    125
    2

    YES!! but....The 7 seg display is showing the display for 14,13, and 12 only over and over.no 9, no 8, no 7 nothing ....just these 3 patterns over and over. I would love to show a schematic but i dont know how and my regular digital camera is broken to take a pic of the circuit.
    another piece of info ........i just made the D input ( to the BCD to 7 seg decoder ) low and now it counts down from 7 to 6 to 5 to 4 and back to 7. the digits are displaying properly.

    141312.png
     
    Last edited: Nov 25, 2013
  14. Nathan Hale

    Thread Starter Active Member

    Oct 28, 2011
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    here is what is am trying to do
    counterup.png
     
  15. Austin Clark

    Member

    Dec 28, 2011
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    First, triple-check that you have everything connected properly. Check each pin, the datasheets, the orientation of the ICs, power strips, etc;
    Also, be sure that all unused pins are either pulled HIGH or LOW.
     
  16. MrChips

    Moderator

    Oct 2, 2009
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    So your counter is counting backwards.
    Connect the clocks using Q.

    Make sure your CLR pins are all connected to Vcc.
    Make sure you have 0.1μF and 10μF caps from Vcc to GND.
     
  17. absf

    Senior Member

    Dec 29, 2010
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    7 - 111 "C B A"
    6 - 110
    5 - 101
    4 - 100
    3 - 011
    2 - 010
    1 - 001
    0 - 000

    Looks like you "C" is permanently stuck in logic High. Check the connections between the second F/F !Q output to the Clk input of the 3rd F/F.

    Allen
     
  18. WBahn

    Moderator

    Mar 31, 2012
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    Thank you!

    This schematic is for a ripple binary up counter (not a down counter).

    If you want a down counter, then you need to connect the Q from each bit to the clock for the next bit. That way each bit will toggle when the bit before it goes from a 0 to a 1, which is essentially implementing a borrow operation.
     
  19. WBahn

    Moderator

    Mar 31, 2012
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    Are you SURE it's just 14, 13, and 12? Only three states? That seems odd. Especially when grounding the D input to the decoder results in a cycle of four states. Are you sure one of your states isn't blank (which is state 15)?

    I think this is what you are seeing. The left is with the D connected and the right is with it gounded:

    F - 1111 - 7 - 0111
    E - 1110 - 7 - 0110
    D - 1101 - 7 - 0101
    C - 1100 - 7 - 0100

    Make sure that the two /CLR signals (pins 10 and 13) are tied HI. Though if one of these was floating LO it would make it's bit a 0 and not a 1.
     
  20. WBahn

    Moderator

    Mar 31, 2012
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    I just went and looked at the 74107 data sheet and noticed a couple of things. First, there are two variants, the 74107 and the 74107A. Check to see which one you are actually using because they are clocked differently.

    The 74107A is negative-edge triggered. If you are using this part, then the schematic you posted will act as a down counter because a given bit will change state when the bit before it goes from a 0 to a 1.

    The 74017 is clocked such that the data is captured on the rising edge but the outputs change on the falling edge of the clock. With the inputs tied HI, this effectively makes them falling-edge triggered as far as the behavior at the outputs is concerned.

    So in either case this schematic should behave as down counter.

    Which do you WANT? An up counter or a down counter.
     
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