[PROBLEM]BLOCK RAM inferencing failed

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity memory_data is
 port (di_bus : in STD_LOGIC_VECTOR(15 downto 0);
       ddo_bus : out STD_LOGIC_VECTOR(15 downto 0);
       a_bus : in STD_LOGIC_VECTOR(9 downto 0);
       nce : in STD_LOGIC;
       rd, wr : in STD_LOGIC;
       dready : out STD_LOGIC);
end memory_data;

architecture bhv of memory_data is
 type memory_array_data is array (0 to 31) of STD_LOGIC_VECTOR(15 downto 0);
begin
 dready <= '1';
 process (nce, rd, wr, di_bus, a_bus) is
  variable mem_data : memory_array_data;
begin
  if nce = '0' then
   if rd = '1' then
    ddo_bus <= mem_data(conv_integer(a_bus));
   end if;
   if wr = '1' then
      mem_data(address) := di_bus;
   end if;
  end if;
 end process;
end architecture bhv;