We have not been formally taught anything in VHDL or Xilinx but I know that I will have to in the future so when my class requires me to design a logic circuit I try and use it to just gain familiarity. I created a magnitude comparitor and mapped two buses, dataa and datab to a0 to a3 and b0 to b3 respectively. I want to use the test bench feature to see the waveforms and I can't figure out why my first logic vector goes in and it never changes. Is there something wrong with my syntax or do I misunderstand what a logic vector can do?

Here is the relevant portion of my code:

  tb : PROCESS
   BEGIN
		high <= '1';
		DATAA <= "0001";
		DATAB <= "0010";
		wait for 2 ms;
		DATAA <= "0010";
		DATAB <= "0010";
		wait for 2 ms;
		DATAA <= "0011";
		DATAB <= "0010";
		wait for 2 ms;
		
      WAIT; -- will wait forever
   END PROCESS;

And here is the output I get:

Sorry for such a newb question. I can't figure it out by searching the depths of the internet. Thanks so much in advance.

 

okay, I'm still curious about the answer, but I tried ns and it worked fine. milli seconds is unsupported?

 

It looks like you didn't run your simulation long enough.

You tell the testbench to not change values for 2ms, yet your simulation goes for 1us...

Try simulating for at least 6ms.

 

Aha! Thanks! I figured it was something trivial. I also discovered in this process the importance of vector 3 downto 0 as opposed to 0 to 3. All of my bits were opposite of what I anticipated and that tripped me up for a bit. Thanks again!

 

Aha! Thanks! I figured it was something trivial. I also discovered in this process the importance of vector 3 downto 0 as opposed to 0 to 3. All of my bits were opposite of what I anticipated and that tripped me up for a bit. Thanks again!

Glad you got it figured out.

Just wait until you implement a ROM...