That could be a problem with the post #19 circuit as is. When PB1 (presumed to be a NC switch) is released after the timeout the D-flop will be left in an arbitrary state; so there's a 50% chance the load will stay energised. The CLR input of the D-flop could be fed from point PB via a diode, and grounded via a ~1meg resistor, to overcome this.I don't want it to work the all time
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