Power factor problem

Discussion in 'Homework Help' started by mavromap, Mar 2, 2008.

  1. mavromap

    Thread Starter New Member

    Feb 9, 2008
    6
    0
    The problem is the following:

    The steady-state voltage drop between the load and the sending end of the line is excessive. A capacitor is placed in parallel with the 250 kVA load and is adjusted until the steady-state voltage at the sending end of the line has the same magnitude as the voltage at the load end, that is 2500 V (rms). The 250 kVA load is operating at a power factor of 0.96 lag. Calculate the size of the capacitor in μF if the circuit is operating at 60 Hz.
    I attached a picture of the circuit. Resistor is 1 Ω and inductor's impedance is 8j Ω.

    I spent more than 2 hours on this problem and still I cannot figure out the solution.

    First of all, I think the wording is unclear. What exactly does this part mean: "[The capacitor] is adjusted in until the steady-state voltage at the sending end of the line has the same magnitude as the voltage at the load end"?
    Which exactly is the load end and which is the line end? If the two ends have the same voltage, doesn't this mean that the voltage across the load is zero?

    Anyway, this is what I've done so far:

    A power factor of 0.96 yields an angle θ = 16 degrees.
    I supposed that after adding the capacitor, the voltage across the load becomes \tilde{V}_{L} = 2500\angle0.
    (I use the ~ accent for the rms value.)
    I found the complex power S = 250\angle 16 kVA using θ.
    Then using S = \frac{|\tilde{V}_L|^2}{Z_L} I calculate the impedance of the load Z_L = 25 \angle (-16).
    I plugged this in the equation for the equivalent load impedance after adding the capacitor: Z_{eq} = \frac{Z_C Z_L}{Z_C + Z_L} (since we know f = 60 Hz, we can find ω and from that Z_C).
    So I found one expression for Z_e_q with C in it.

    I also know that, using voltage divider, \tilde{V}_L' = \frac{Z_e_q}{Z_e_q + Z_a_b} \tilde{V}s, where Z_a_b is the equivalent impedance of the resistor and the inductor.

    So here's one problem. We are not given a value for \tilde{V}_s. So I assumed it is just known.

    From this equation I solved for Z_e_q and found an expression with no C in it.

    So I equated the two expressions for Z_e_q and tried to solve for C, but a very messy expression came out, and I didn't even try to continue... I have feeling that C is going to be a phasor!

    So, what went wrong? Thank you very much for your help.
     
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  2. kinyo

    Member

    Jun 6, 2005
    13
    0
    Load end is the load side (on the right). Sending end is the generator side (on the left) with voltage Vs.

    Yes, zero if they are of the same phase angle. But they don't have the same phase angle in this problem. They only have the same magnitude (rms voltage).

    -------
    This is indeed a difficult problem (at least on my part too!, others may have better/easier solution). An educated intuition would dictate that the resulting reactive power of combined load and capacitor should give a leading power factor, not lagging. No lagging power factor could satisfy the |Vs | = |VL | condition.

    So a sugggested approach is to find the leading Q to satisfy the given condition.

    A quick check with a simulator gave the capacitance at 59.25 uF. You may now do your calculations if indeed it would satisfy the condition. This is just to make sure that when you finally determine the capacitor value analytically, you know it is correct.

    Good luck.
     
  3. mavromap

    Thread Starter New Member

    Feb 9, 2008
    6
    0
    kinyo, thanks for your reply.

    I finally found a solution. You consider the currents through the load and through the capacitor (I_C), then using KCL you compute the current in the line. Then, using KVL we express V_s in terms of I_C and since you want |V_s| to be equal to 2500 V, we end up with a quadratic equation of I_C . Solving (and choosing the smallest solution to minimize the current through the line) you calculate the reactance X_C = \frac{V_s}{I_C} and from that the capacitance C = \frac{1}{|X_C|\omega} .

    I still don't know the difference between a lagging power factor and a leading pf. Can you please explain it to me?

    Thanks
     
  4. kinyo

    Member

    Jun 6, 2005
    13
    0
    Lagging and Leading refers to the current phasor relative to the voltage phasor. When the current lags the voltage, it means the circuit is inductive. When the current leads the voltage, it means the circuit is capacitive.

    In your problem, with the addition of the capacitor, the combined phasor currents (vector addition of load and capacitor currents) results in a current that leads the voltage at the load, hence the combination is a net capacitive load. However, at the generator side, you will find that the current lags the generator voltage, hence, the generator sees an inductive load.

    This concept is easily understood if you draw the phasors involved. With the load voltage as your reference (assigned with zero degrees), the load current phasor will have -16.26 degrees, the capacitor current phasor will be at +90 degrees. If you add the two phasors, you'll find that their sum will have a positive angle, hence, leading (relative to the load voltage).

    And if you further plot for the generator voltage, Vs, you'll find that the current lags the generator voltage phasor.

    I hope this helps.

    Now I'm hoping to see your solution.
     
  5. mavromap

    Thread Starter New Member

    Feb 9, 2008
    6
    0
    Thanks a lot, it was pretty clarifying.
     
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