# power dissipation CMOS

Discussion in 'General Electronics Chat' started by ConfusedMuchMor, Jan 11, 2009.

1. ### ConfusedMuchMor Thread Starter New Member

May 18, 2008
2
0
I'm trying to work out the power dissipation of a CMOS device74HCT08 from the data sheet I get this formula, I don't understand the fi & fo(I surmise this means Inputs may be changing numerous times without reaching a state that affects a change at the outputs) If I'm right in this assumption what duty cycle/ ratio do you use for calculation?
PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo)

fi = input frequency in MHz;
fo = output frequency in MHz;
å (CL ´ VCC2 ´ fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.

2. ### Wendy Moderator

Mar 24, 2008
20,766
2,536
f is frequency. C is the capacitance you are feeding, the built in capacitance for the circuit. This could be hard to figure out, since you don't really know this value just looking at it. You could try feeding a bogus number, such as 10pF, to see what the equation pops out.

CMOS gate usually only use power if they switch, Just sitting there it is in picoamps. During switching the 2 CMOS transistors are conducting, that and they have to force the capacitance on the output to change states.