Possible reasons / root causes for Impedance mismatch of Voltage Test Points in assembled PCB

Discussion in 'The Projects Forum' started by vijethahn, Nov 14, 2014.

  1. vijethahn

    Thread Starter New Member

    Nov 14, 2014
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    Hello there,

    I am Vijetha H.N, working in an organization as a PCB Design Engineer. I have a very general query regarding board testing.
    When we get the assembled boards, we usually do Impedance testing; we measure the impedance of each voltage test points w.r.t Ground to confirm that the voltage points are not shorted to Ground.
    During mass production, we usually consider the impedance values observed in 1st 1 or 2 boards as reference for rest of the boards.
    In case If we find a variation in the Impedance value in any of the board what will be the probable causes for the mismatch ? For example If I observe 1.5 K OHM for a voltage test point in 5 boards and If I observe 500 OHM of value in 6th board for same test point, what will be the possible root causes for this mismatch ? Please list down all possible root causes for Impedance mismatch issues in the Assembled PCB for a same test point? This will be helpful in quick debug of the boards during mass production.

    Regards,
    Vijetha H.N
     
  2. Papabravo

    Expert

    Feb 24, 2006
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    I'm not that familiar with this board testing method, and I have some questions.
    Is it done with power ON or power OFF?
    What type of circuitry is on the board?
    What leads you to believe that the impedance of a test point is constant under the test conditions?
     
  3. vijethahn

    Thread Starter New Member

    Nov 14, 2014
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    The Impedance Test will always be done in Power OFF condition to make sure that no Voltage net is shorted to GROUND due to improper soldering/component assembly/fabrication.
    This is a huge board with FPGAs, CPLDs, Clcok circuits, Memory circuits etc. Here I am concerned with the Power circuits which has a number of power regulator and supporting cicuits.
    Since the design remains the same for all boards, the Impedance values should remain same. if it varies it is considered as issue. Here I want to know what are the reasons for this variations?
     
  4. ErnieM

    AAC Fanatic!

    Apr 24, 2011
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    We do testing like that here using a flying probe and a ground clip. A program drives the tip to testpoints and compares the resistance (measured both ways +/-) to stored values and tollerances.

    It is not an exacting test as there are some failure modes that will fly right thru this. For example, it is pretty damn useless for detecting missing capacitors. But it is pretty good at finding other gross errors such as shorts, missing resistors, wrong value resistors. It even is pretty good at finding missing IC's by their internal ESD diodes.

    As far as making a decision failure tree just from a resistance reading you are out of luck. It is entirely dependent on the particular board and the circuitry used there. For one, this may be due to incorrect resistors, or it may be a perfectly fine board with a trimmer pot adjusted differently from the others.

    If I have 5 boards that do one thing and another that does something else I put the 5 in the GOOD bin, then sit down with a schematic, layout, ohmmeter, and a magnifying glass to worry out what may be causing this 6th board to act differently.

    Here's another aside for you: if I had to test something but was limited to doing just one test for functionality I would power it on and measure the current it takes. If the current is too low something is missing. If the current is too high there is something extra (shorts count as "extra").

    Normally you do more than one test, and normally I do include current. There was one case where a board would pass every test except the current was too low. The failure here was an open zener diode, and without that diode a CMOS timer would see 28V for it's power. While CMOS may work for a while with 28V it will soon fail.

    One hopes all the failures occure at my plant not at my customer. Without this one simple test...
     
  5. vijethahn

    Thread Starter New Member

    Nov 14, 2014
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    Thats very good point about current test. i have never tried that.

    I used to check following things:
    1. Whether all DNP (Do Not Populate) components are not mounted
    2. There is no capacitor mounted in place of resistor and vice versa (this will be done through visual inspection, magnifying glass, layout schematics etc.)
    3. Check the resistance values. It need not be the same as the equivalent resistance value matters. But it should not be more than the rated value or it should not be 0 for non zero resistors.
    4. Check if the IC pins are properly soldered.
    5. Check for the shorts between the IC pins (check with nearby pins) for TSSOP, SOIC packages. But it will be difficult to observe for QFN packages and/or BGA package ICs.
    6. If any doubt of short between power pin and adjacent pin of a BGA package IC is found (visually) then better to do re flow or solder touch up and check.
    7. For BGA ICs, If none of the debugging techniques does not work, better take X-ray and observe for Solder contact or solder short.
    8. If the Voltage net with impedance mismatch is running through any inductor or ferrite bead , better check the impedance across the Inductor/ferrite bead (expecting short or within 1 OH of impedance).
    9. Repeat from point 1 to 7 for all the parts coming after the series inductor or ferrite bead on the voltage net.

    These are the points I learnt while debugging a card (did not try with the point #7). But still I have solved issues with couple of cards. But in 2 more cards, I am still not finding the reason for Impedance variation issue. Thats why I posted here to know is there any other methods to challenge this issue and to know am i missing anything here. However I consider this current test and check once. if any on have other suggestions/feedbacks please mention here.

    Regards,
    Vijetha
     
  6. Papabravo

    Expert

    Feb 24, 2006
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    I would be extremely reticent about testing CMOS devices with this method. Even a small potential on an un-powered device input can punch a hole in the SiO2 gate insulator. Even if the damage is not immediately apparent, it will precipitate an eventual failure.
     
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