Possible my AT91SAM7X is locked. How to Release?

Discussion in 'Embedded Systems and Microcontrollers' started by dor, Dec 12, 2009.

  1. dor

    Thread Starter Active Member

    Feb 20, 2009
    I think that my AT91SAM7X512 uC is locked.

    I reached this conclusion since that my IDE (or, to be precise, the JLink software) tells me that my processor can't be halted. (after clicking the Debug button)
    Following this message, I've searched in this JLink PDF the word "halt", and found:

    Then, I remembered that there's no PLL circuit in my board!
    That PLL circuit should be connected to the PLLRC pin (num. 99), as seen in Atmel's development kit PDF.
    Furthermore I noticed that the JLink software configures the MCU to use the PLL clock prior to downloading the binary to the Flash memory. In other words, it configures the PMC_MCKR register to have the value 0x7 !

    What should I do?

    Except the PLL, my board schema is the same as Atmel's development kit (excluding peripherals).

    I appreciate your time & effort.
  2. dor

    Thread Starter Active Member

    Feb 20, 2009
    I solved the problem by connecting the RC circuit to the PLLRC pin.

    But now a new problem arises:

    When the processor executes the code while in debug mode, it causes to a Prefetch Abort exception. (sometimes a SWI exceptions occur too)

    I noticed that when assigning a breakpoint prior to a PMC_PCER register modification, the exception does not occur and the processor executes the code well.
    How does a breakpoint manage to fix the problem? Is it the delay?

    Before the PMC_PCER register modification, the code changes MCK (via PMC_MCKR) to the value of Main Clock.
    Perhaps the clock isn't stable so a delay is required? It doesn't make sense, because that I wait for MCK to be ready (by validating the value of MCKRDY in PMC_SR).

    Sorry for not bringing any code, it is not on my PC. I'll be able to add code later, if required (?).

    I read in this topic that a connected JTAG cable may cause a Prefetch Abort.
    But how can I debug without connecting the JTAG?

    Thank you!
  3. ftsolutions

    Active Member

    Nov 21, 2009
    Is your J-Link /software configured for adaptive clocking, and do you have the TCK RTCK pins connected? IF you run J-Link Commander, what does it report on the CPU ? What development IDE are you using - IAR, Keil ??
  4. dor

    Thread Starter Active Member

    Feb 20, 2009
    What does "adaptive clocking" means?

    All the JTAG pins are connected.

    J-Link (CLI) does recognize the CPU/micro-controller without any problems.

    EDGE is my development IDE.
  5. dor

    Thread Starter Active Member

    Feb 20, 2009
    I wrote a 4 rows C code that changes the source of the MCK clock: from PLL to Main Clock.

    The change wasn't according to the DS requirement (written in the Programming Sequence section of the PMC), thus weird problems occurred.

    So I added some bitwise operations that solved the problems.