# Positive-edge triggered JK flip-flop

Discussion in 'Homework Help' started by 60remember, Jul 8, 2013.

1. ### 60remember Thread Starter New Member

Jul 6, 2013
4
0
Hello,

I'm trying to understand the attached schematic. It's supposed to be a positive-edge triggered JK flip-flop. As far as I know, it means that it's only reacting to commands during the positive-edge. So if there was a short jump command during CLK = 0 and Q = 0, nothing should happen - right?

However, the given schematic shows a positive-edge triggered JK flip-flop (made of D-flip flops). Now imagine Q = 0 and C = 0. Meanwhile a short J-command occurs. Wouldn't that mean: Immediately, the master-FF changes to 1? And as soon as C = 1, this state is passed to the slave?

I'm really confused, because this would mean you could change the flip-flip's state by sending a command during C = 0 - doesn't it?

60remember

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2. ### LDC3 Active Member

Apr 27, 2013
920
160
What do you mean by "short jump command"? I don't understand.
Also, what do the symbols on the gates represent (≥1, &, 1)?

3. ### 60remember Thread Starter New Member

Jul 6, 2013
4
0
What I mean is a jump command, ending before there is an edge - the red one in this diagram. I'm not sure how Q is going to behave: Green is what I would actually expect from a JK-FF, orange is what I would guess this circuit does. But this can't be true - it wouldn't be a JK flip-flop anymore, would it?

I forgot about the symbols, sorry: & means AND, ≥1 means OR, these small circles mean negation. So a 1 with a circle simply means negation.

edit: Master and slave are both gated D latches, by the way.

• ###### jk2.png
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Last edited: Jul 8, 2013
4. ### LDC3 Active Member

Apr 27, 2013
920
160
I will need to check out the logic when I get home (in about 5 hr). Maybe someone else can help sooner.

5. ### WBahn Moderator

Mar 31, 2012
17,446
4,699
I have no idea what a "J-command" is.

What does it mean to be positive-edge triggered. It means that the OUTPUTs only change state at the positive edge of the clock. So when you say

But doesn't "as soon as C=1" describe the positive edge of the clock?

You need to ask two questions:

Q1) Is there any change on the non-clock inputs that can result in a change in the final Q outputs except at the positive edge of the clock?

Q2) Is there any sequence of changes on the non-clock inputs that can happen prior to the positive edge of the clock that will make it so that the final Q outputs are not determined solely by the state of the other inputs just prior to the positive clock edge?

6. ### LDC3 Active Member

Apr 27, 2013
920
160
I believe there is a problem with your JK schematic.