Port Address Decoder Problem

Discussion in 'General Electronics Chat' started by parkhid, Dec 15, 2012.

  1. parkhid

    Thread Starter New Member

    Dec 20, 2010
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    Hi All, Please Take look at the picture below :

    [​IMG]

    For generating The RD4F And WR4F Commands , Why the designer used the OR Gates ? If the WR and RD Signals are both active , We will have an overwriting .

    How this circuit will work ?

    It is supposed that the IO is active not Memory access.
     
  2. ErnieM

    AAC Fanatic!

    Apr 24, 2011
    7,386
    1,605
    The signals are negative logic, or zero = true. If you take the time to draw a simple truth table you will see the output is valid only for an OR gate function.
     
    parkhid likes this.
  3. parkhid

    Thread Starter New Member

    Dec 20, 2010
    7
    0
    Thanks .... ErnieM
     
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