Hello,
Assume the following basic PNP switching circuit as shown below. If the input of the first NPN transistor goes HI then the output of that transistor goes LO. If I connect +Vcc directly to the collector of the PNP transistor at DC2 then per the table on the far right the emitter of the PNP transistor goes HI. How? Isn't the PN junction reversed bias? The table states the emitter of the PNP goes HI and indeed in the application it does go HI but i don't understand why?
Assume the following basic PNP switching circuit as shown below. If the input of the first NPN transistor goes HI then the output of that transistor goes LO. If I connect +Vcc directly to the collector of the PNP transistor at DC2 then per the table on the far right the emitter of the PNP transistor goes HI. How? Isn't the PN junction reversed bias? The table states the emitter of the PNP goes HI and indeed in the application it does go HI but i don't understand why?