Hi to all,
I've to study following circuit ( in attachment )
For Vi varing from 0v to 3.5V
I'm able to determine following working regions:
( Vi > 0V AND Vi < 0.7V ) ==> Q1 = CUT_OFF , M2 = LIN
After that I'm expecting that Q1 turn ON this happens when Vi >= 0.7V
After that I impose current balance:
Ic ( for Q1 ) = Isd ( for M2 PMOS )
Vi >= 0.75V Q1 must be ON
3.5 - Vu <= 3.5 - Vi - |Vtp| M1 must be LIN
I get Vi = 1.3503 Vu = 1.95035
( Vi > 0.7V AND Vi < 1.3503V ) ==> Q1 = AD , M2 = LIN
After that for Vi > 1.3503 transistor M2 goes to SAT, if I keep on to increase Vi and I'm expecting that Q1 goes
to SAT when this happens Vu = 0.2V, after M1 will TURN OFF for 3.5 - Vi < | Vtp | = 2.9V
I can resume this:
( Vi > 0V AND Vi < 0.7V ) ==> Q1 = CUT_OFF , M2 = LIN
( Vi > 0.7V AND Vi < 1.3503V ) ==> Q1 = AD , M2 = LIN
( Vi > 1.3503V AND Vi < Vx ) ==> Q1 = AD , M2 = SAT
( Vi > Vx AND Vi < 2.9V ) ==> Q1 = SAT , M2 = SAT
( Vi > 2.9V ) ==> Q1 = SAT , M2 = OFF
Here I've two question that I'd like to solve:
1. How I can to find out Vx. I cannot use current balance because Isd ( for PMOS ) doesn't depend from Vsd. So I can have any voltage Vsd. For have Q1 SAT Vsd must be equal to 3.5 - 0.2 = 3.3. I'm expecting to go the Vsd, Isd
characteristic and find the first curve ( minor value of Vsg ) the support following configuration. But in this
exercise don't have that value.
2. When I simulate with Pspice is it correct to shortcut BODY pin with SOURCE pin for both NMOS and PMOS
transistor?
Thank you very much for your help!
Happy New Year!
Regards
Maurizio
I've to study following circuit ( in attachment )
For Vi varing from 0v to 3.5V
I'm able to determine following working regions:
( Vi > 0V AND Vi < 0.7V ) ==> Q1 = CUT_OFF , M2 = LIN
After that I'm expecting that Q1 turn ON this happens when Vi >= 0.7V
After that I impose current balance:
Ic ( for Q1 ) = Isd ( for M2 PMOS )
Vi >= 0.75V Q1 must be ON
3.5 - Vu <= 3.5 - Vi - |Vtp| M1 must be LIN
I get Vi = 1.3503 Vu = 1.95035
( Vi > 0.7V AND Vi < 1.3503V ) ==> Q1 = AD , M2 = LIN
After that for Vi > 1.3503 transistor M2 goes to SAT, if I keep on to increase Vi and I'm expecting that Q1 goes
to SAT when this happens Vu = 0.2V, after M1 will TURN OFF for 3.5 - Vi < | Vtp | = 2.9V
I can resume this:
( Vi > 0V AND Vi < 0.7V ) ==> Q1 = CUT_OFF , M2 = LIN
( Vi > 0.7V AND Vi < 1.3503V ) ==> Q1 = AD , M2 = LIN
( Vi > 1.3503V AND Vi < Vx ) ==> Q1 = AD , M2 = SAT
( Vi > Vx AND Vi < 2.9V ) ==> Q1 = SAT , M2 = SAT
( Vi > 2.9V ) ==> Q1 = SAT , M2 = OFF
Here I've two question that I'd like to solve:
1. How I can to find out Vx. I cannot use current balance because Isd ( for PMOS ) doesn't depend from Vsd. So I can have any voltage Vsd. For have Q1 SAT Vsd must be equal to 3.5 - 0.2 = 3.3. I'm expecting to go the Vsd, Isd
characteristic and find the first curve ( minor value of Vsg ) the support following configuration. But in this
exercise don't have that value.
2. When I simulate with Pspice is it correct to shortcut BODY pin with SOURCE pin for both NMOS and PMOS
transistor?
Thank you very much for your help!
Happy New Year!
Regards
Maurizio
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