PMOS current mirror - Small signal analysis - Why is Vsg = 0v?

Discussion in 'Homework Help' started by KaiL, Sep 28, 2016.

  1. KaiL

    Thread Starter Member

    Aug 30, 2014
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    upload_2016-9-29_0-29-21.png

    The one in red box , why is Vsg2 = 0V?
    Vsg2 = Vs - Vg --> Vs = 0 since it is ground but what about vg?
     
  2. AlbertHall

    Well-Known Member

    Jun 4, 2014
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    As the red writing by the red box says, it is at a fixed DC voltage and there can be no AC voltage there so it acts for AC signals the same as ground or Vdd.
     
  3. KaiL

    Thread Starter Member

    Aug 30, 2014
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    0
    upload_2016-9-29_15-39-51.png
    Actually I still don't get it :(
    I am trying to do a circuit analysis on the red box but I am not sure why it is 0 V for Vsg2
    Vs=0 V since it is grounded but Vg isnt equal to Vout?
    So Vs-Vg = Vsg2 --> Vsg = 0 - Vout???

    Did I do it wrongly for analysis part?
     
  4. AlbertHall

    Well-Known Member

    Jun 4, 2014
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    You are thinking DC, but the red box is considering AC. There is zero signal voltage on the gate of the top FET.
     
  5. Jony130

    AAC Fanatic!

    Feb 17, 2009
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  6. Russmax

    Member

    Sep 3, 2015
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    Saying vsg2 = 0 means 2 things:
    1) M3 and IREF can be replaced by a DC voltage source from source to gate of M2.
    2) DC voltage sources are shorted for small-signal analysis.
    Therefore, vsg2 = 0
     
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