plz ...Verilog-HDL an up/down BCD counter

Discussion in 'Embedded Systems and Microcontrollers' started by SQU, Apr 27, 2009.

  1. SQU

    Thread Starter New Member

    Apr 27, 2009
    1
    0
    Hi

    plz help me how can i write

    verilog-HDL an up/down BCD counter

    i make 4 function for up
    and 4 for down

    but how can i write them in verilog-HDL


    can i use assign in if statement ??
    if(up==1)
    {
    assign f1= xxxxx;
    assign f2= xxxxx;
    assign f3= xxxxx;
    assign f4;= xxxxx;
    }
    if(down==1)
    assign g1= xxxxx;
    assign g2= xxxxx;
    assign g3= xxxxx;
    assign g4;= xxxxx;
    }




    plz see attachments
    i want to write Verilog-HDL for this diagram

    :confused::confused::confused:


    Thanks ....



     
  2. Wtech

    New Member

    Apr 27, 2009
    8
    0
    According to your diagram this will done by behavioral modeling,

    always@(posedge clk) //if positive edge trigger as in your case
    begin
    If (up == 1)
    f = f + 1; //where f is 4bits should be initialized
    else If(down == 1)
    g = g+1; //where g is 4bits output
    end
     
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