hi to every one i have a problem with this homework is my last project for my university and i must give it until the next week and the problem is very big!!thank's a lot!!! George, study group 188 1. With the aid of a synchronous sequential circuit implement a finite state machine with inputs a, b and output z according to the following transition and output tables. Employ an appropriate method of minimization and coding internal states. Verify the correctness of the designed circuit by marking the logic values in the schematic diagram of the circuit. Verify in this way two total states of the resulting automaton: one stable (the next state is equal to the present state) and the other unstable (the next state differs from the present state). Print the circuit scheme twice, once for each of the states mentioned above. Mark all wires with logic values (0,1,x). Indicate, which total state is represented by the scheme. \ba| transition table Qi\ | 00 01 10 -------------------- Q0| Q14 Q9 Q11 Q1| Q6 Q9 Q13 Q2| Q14 Q14 Q11 Q3| Q4 Q0 Q11 Q4| Q12 Q0 Q13 Q5| Q3 Q3 Q5 Q6| Q9 Q0 Q6 Q7| Q4 Q12 Q5 Q8| Q7 Q1 Q8 Q9| Q3 Q3 Q7 Q10| Q5 Q0 Q8 Q11| Q8 Q8 Q13 Q12| Q4 Q1 Q2 Q13| Q10 Q8 Q2 Q14| Q7 Q1 Q14 output table 00 01 10 0 1 1 0 1 1 1 0 1 0 0 1 0 0 1 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 0 0 Use D(FDC) flip-flops. 1. Use gates NAND and NOR only. 2. External input signals are available in direct form only. 3. Assume that component delays (latencies) are equal to delays (latencies) shown in the home page of project. 2. Derive the maximum applicable clock frequency under following assumptions: the input state can change in the interval < T , T + 3ns >, where T is the time when falling edge of the clock signal appears. Correct output state should last for at least 3 ns. The written report has to consist of: 1. this project specification, 2. the coding of internal states, 3. coded transition and output tables, 4. karnaugh maps for excitation signals of flip-flops and for external output signals, 5. boolean expressions in minimal SOP forms for the above signals, 6. the scheme of the designed circuit, 7. computation of the maximum applicable clock frequency.