PLL phase error in steady state

Discussion in 'General Electronics Chat' started by d_sl4y3r, Sep 5, 2010.

  1. d_sl4y3r

    Thread Starter New Member

    Oct 27, 2009
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    Is it possible to determine the phase error of a PLL in steady state knowing only:

    - open loop dc gain value (kv)
    - vco gain (kd)
    - the phase detector is a 4 quadrant multiplier
     
  2. t_n_k

    AAC Fanatic!

    Mar 6, 2009
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  3. d_sl4y3r

    Thread Starter New Member

    Oct 27, 2009
    4
    0
    Thank you for your answer.
    I will take a look at this file =)
     
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