PLL loop filter design

Discussion in 'Wireless & RF Design' started by veerasamy, Oct 9, 2009.

  1. veerasamy

    Thread Starter New Member

    Oct 7, 2009
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    Please help on how to design PLL loop filter for specific loop band width? ( what is loop bandwidth anyway?). I have charge pump current and VCO sensitivity as input.

    Thanks &Regards,
    V.Veerasamy
     
  2. t_n_k

    AAC Fanatic!

    Mar 6, 2009
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  3. hgmjr

    Moderator

    Jan 28, 2005
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    What is the part number of the PLL device have you chosen to use? And how are you planning to use the PLL?

    hgmjr
     
  4. veerasamy

    Thread Starter New Member

    Oct 7, 2009
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    Thanks t_n_k. To hgmjr: I am using PLL with integrated VCO (AD4350).
     
  5. Tesla23

    Active Member

    May 10, 2009
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  6. hgmjr

    Moderator

    Jan 28, 2005
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    Are you refering to the ADF4350 made by Analog Devices? I could not locate any information on the AD4350.

    hgmjr
     
  7. veerasamy

    Thread Starter New Member

    Oct 7, 2009
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    to hgmjr: Yes i am using ADF4350.
    to Tesla23: I am using AdsimPLL. but in AdsimPLL it assumes phase detector frequency and channel spacing are same. For me they are different
     
  8. Tesla23

    Active Member

    May 10, 2009
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    If you are doing a Fractional-N design then make sure that you select this on ADIsimPLL, then you can select the modulus on the Chip page, and you will see the channel spacing is different to the PD frequency.

    As an example, if you choose the ADF4350 on the first page of the wizard and accept all the default parameter values you will get a Fractional-N design where the channel spacing is different to the PD frequency.
     
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